Rambus Demonstrates Industry-first PCIe 5.0 Digital Controller IP for FPGAs
Rambus Demonstrates Industry-first PCIe 5.0 Digital Controller IP for FPGAs
SAN JOSE, Calif. – Aug. 30, 2021 – Rambus Inc. (NASDAQ: RMBS), a premier chip and silicon IP provider making data faster and safer, today announced that Rambus has demonstrated its PCI Express® (PCIe) 5.0 digital controller IP on leading FPGA platforms. PCIe 5.0 performance at 32 GT/s in FPGAs using a soft controller is an industry first, and another demonstration of technical leadership from Rambus. This capability expands the use models of FPGAs by enabling multi-instance, switching and bridging applications and accelerates the performance of FPGAs used in defense, networking, and test and measurement markets.
“We’ve achieved a new industry benchmark with the demonstration our PCIe 5.0 controller operating at 32 GT/s on popular FPGA platforms,” said Scott Houghton, general manager of Interface IP at Rambus. “With the growing importance of FPGAs in markets from defense to the data center, this solution developed by the newly-acquired PLDA team expands the Rambus portfolio and offers the next level of performance for mission-critical applications.”
Features of the Rambus PCIe 5.0 Digital Controller:
- Verified on leading FPGA platforms
- Supports up to 32 GT/s data rates
- Backwards compatible to PCIe 4.0 and 3.1/3.0
- Supports Endpoint, Root-port, Dual-mode, and Switch-port configurations
- Supports up to 64 Physical Functions (PF), 512 Virtual Functions (VF)
- Supports AER, ECRC, ECC, MSI, MSI-X, multi-function, crosslink, DOE, CMA over DOE, and other optional features and ECNs
For more information on the Rambus digital controller, please visit rambus.com/interface-ip/controllers/. Or to find out more details on Rambus Interface IP, including our PHYs and Controllers, please visit rambus.com/interface-ip.
Related Semiconductor IP
- PCIe 5.0 Controller
- PCIe 5.0 Controller with AXI
- PCIe 5.0 (Gen5) Standard Controller with AMBA bridge II
- PCIe 5.0 (Gen5) Standard Controller EP/RP/DM/SW 32-128 bits with AMBA bridge
- PCIe 5.0 (Gen5) Standard Controller EP/RP/DM/SW 32-128 bits
Related News
- Cadence Achieves PCIe 5.0 Specification Compliance for PHY and Controller IP in TSMC Advanced Technologies
- Intel Launches Agilex 7 FPGAs with R-Tile, First FPGA with PCIe 5.0 and CXL Capabilities
- Silicon Proven PCIe 5.0 PHY and Controller IP Cores in 12nm to Revolutionize Connectivity solutions
- DI3CM-HCI, A High-Performance MIPI I3C Host Controller IP Core for Next-Generation Embedded Designs
Latest News
- Avalanche Technology and NHanced Semiconductors Deliver the Industry’s First Truly Space Grade MRAM Boot Solution for RadHard System-in-Package Integration
- Marvell Completes Acquisition of XConn Technologies
- Rambus Announces Departure of Chief Financial Officer
- AI Elevates Production Management’s Importance in the ASIC Value Chain
- Cadence Unleashes ChipStack AI Super Agent, Pioneering a New Frontier in Chip Design and Verification