MIPS, GlobalFoundries Bet on Physical AI
By Aalyia Shaukat , EE Times | March 3, 2026

MIPS has made some waves in the embedded processor IP community, especially with its recent acquisition of Synopsys’s ARC processor IP business. The company has made a major comeback since filing for bankruptcy in 2020 and emerging from the downturn, shifting its focus from Microprocessor without Interlocked Pipelined Stages (MIPS) to RISC-V architecture. The company heralded the MIPS instruction set with massive success, helping accelerate it’s physical AI roadmap. “We’ve got 200 million SoCs today in autonomous vehicles with long-standing customers,” James Prior, head of marketing at MIPS, told EE Times at CES 2026.
The move to RISC-V
Since its foundational MIPS architecture was introduced in 1985 via the R2000/R3000, MIPS has introduced seven versions of MIPS cores, and since 2022, the eighth generation has been RISC-V. “Our eighth generation of products is our first generation of RISC-V,” Prior said. He referenced the company’s long-standing customer Mobileye, which has already released six generations of its EyeQ product line and recently announced EyeQ7 using the new MIPS RISC-V technology. “EyeQ6 is used in 1,200 different car models across 50 different global OEMs. That’s 75% of ADAS in the actual market.”
To read the full article, click here
Related Semiconductor IP
- 5G-NTN Modem IP for Satellite User Terminals
- 14-bit 12.5MSPS SAR ADC - Tower 65nm
- 5G-Advanced Modem IP for Edge and IoT Applications
- TSN Ethernet Endpoint Controller 10Gbps
- 13ns High-Speed Comparator with no Hysteresis
Related News
- MIPS S8200 Delivers Software-First RISC-V NPU To Enable Physical AI at the Autonomous Edge
- GlobalFoundries to Acquire Synopsys’ Processor IP Solutions Business, Expanding Capabilities to Accelerate Physical AI Applications
- MIPS Drives Real-Time Intelligence into Physical AI Platforms
- MIPS Takes System-Level Approach to Physical AI
Latest News
- MIPS, GlobalFoundries Bet on Physical AI
- IPrium releases LunaNet AFS LDPC Encoder and Decoder for Lunar Navigation Satellite Systems
- Quintauris Introduces Altair: The Unified RISC-V Profile for Embedded Systems
- IAR accelerates SDV development with Infineon DRIVECORE bundles and AURIX™ RISC-V Debug capabilities
- Ceva Launches PentaG-NTN™ 5G Advanced Modem IP, Enabling Satellite-Native Innovators to Rapidly Deploy Differentiated LEO User Terminals