Will More-than-Moore Take Off in China?
By Mo Dakang
EETimes (August 20, 2019)
Most semiconductor enterprises in China are focusing on their survival and profit. It's impractical to force them to keep following Moore's Law or trying the IDM model for memory volume production.
Professor Bo Zhang of the University of Electronic Science and Technology of China recently suggested that "More than Moore" will become an important opportunity for the Chinese semiconductor industry. Professor Zhang's unique insights on this topic are now attracting interest from the industry.
The “More-than-Moore” concept seems new. It's not. Professor Zhang said that it is, actually, nothing more than one of the three directions of Moore's Law.
Professor Zhang refers to the “More-than-Moore process” as “non-size dependent.” It describes the improvement of the value or performance of the device, not by the size reduction, but by the increase of functions.
Moore's Law has governed the semiconductor industry for more than 50 years, shrinking the size of transistors and enlarging the diameters of wafers, with the former playing a critical role.
But Moore’s Law has its limitations. It worked in an era when increasing the density of transistors reduced costs. Moore’s Law, however, failed to predict the greater power consumption at the cost of improved transistor performance. This has prompted the industry in recent years to look at other dimensions of the Law – namely, “non-size dependent" processes.
Why More-than-Moore now?
To read the full article, click here
Related Semiconductor IP
- Root of Trust (RoT)
- Fixed Point Doppler Channel IP core
- Multi-protocol wireless plaform integrating Bluetooth Dual Mode, IEEE 802.15.4 (for Thread, Zigbee and Matter)
- Polyphase Video Scaler
- Compact, low-power, 8bit ADC on GF 22nm FDX
Related News
- European report considers 450-mm More-than-Moore fab
- More-than-Moore Will Lead, Argues GloFo's Wijburg
- Shanghai Seeks 'More-than-Moore' in Silicon Valley
- PLDA Announces Second Annual "PLDA Design Day", in Shanghai, China - a Free Design Workshop, 100% Focused on PCIe Design
Latest News
- How hardware-assisted verification (HAV) transforms EDA workflows
- BrainChip Provides Low-Power Neuromorphic Processing for Quantum Ventura’s Cyberthreat Intelligence Tool
- Ultra Accelerator Link Consortium (UALink) Welcomes Alibaba, Apple and Synopsys to Board of Directors
- CAST to Enter the Post-Quantum Cryptography Era with New KiviPQC-KEM IP Core
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology