Dolphin Integration introduces a new Panoply of Silicon IPs for reducing the 65 nm silicon area up to 10%

Meylan, France – June 25, 2010.  Designers of cost-optimized SoCs now can take advantage of the High Density Panoply to increase the density of their SoC up to 10%.

The Dolphin Integration High Density Panoply for the 65 nm technological process comprises a complete solution for the whole logic design to address the cost reduction challenge at the architectural level.

The HD Panoply integrates:

• The 6 track Standard Cell Library, HD-BTF
• The Aura architecture for One Port and Two Ports Register Files from 128 bits up to 32 kbits
• Single Port and Dual Port RAMs Haumea from 16 kbits up to 512 kbits
• Metal Programmable ROMs from 1kbit up to 6MBits known as the Haumea and Phoenix architectures
• Application and Integration support to ensure the highest density at SoC level

The High Density Panoply is a real star for cost reduction:

• Depending on the instance capacity, the spRAM Haumea is up to 15% denser than contender’s solutions
• Embedding the patent pending Access Strip, the dpRAM Haumea is up to 30% denser than traditional dpRAM
• Thanks to the patented “two-in-one” high density bit-cell, instances generated with the Phoenix architecture for ROM are 2 times smaller than alternative ROM
• The Aura architecture for Register Files is designed to be mixable in the logic blocks among the rows of the Standard Cell Library
• The Standard Cell Library HD-BTF is 5% to 10% denser than a typical 7 track Standard Cell Library after P&R

Do you feel skeptical about the achievement of such performances on your own design? Contact us to take advantage of our suggested Application Schematics, Prescriptions and Consistency of Products for a density-optimized architecture: ragtime@dolphin.fr

More information on the key benefits and performances of the High Density Panoply is available directly on the Brochure:

http://www.dolphin.fr/flip/ragtime/ragtime_bestwith.html

About Dolphin Integration

Dolphin Integration is up to their charter as the most adaptive creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation and Foundry independence. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components, resilient to noise and drastic for low power-consumption, together with engineering assistance and product evolutions customized to their needs.

For more information about Dolphin, visit: www.dolphin.fr/sesame