Chipidea's 0.13µm Low Power I&Q ADC designed for DVB-H/DMB systems excels in Silicon

September 5, 2005 -- CHIPIDEA´s 0.13µm Low Power I&Q ADC designed for DVB-H/DMB systems excels in Silicon CHIPIDEA´s 0.13µm Low Power 10-bit I&QADC was designed for Handheld Digital TV receivers supporting the emerging DVB-H video standard. This is an excellent Analog-to-Digital interface for receivers in portable systems, such as PDAs, phones, and PMPs. The CI3611ul is successfully embedded in an application specific SoC. This I&Q ADC IP core is also available in 90nm CMOS upon request.

The following block diagram illustrates the CI3611ul:


It is composed of a dual fully differential high speed low-power pipelined ADC core suitable for receive channels in I&Q configuration.

Dedicated S/H circuits are built-in to provide direct DC coupling with common mode voltage from 0.5V to 2V, and offering an optional single-ended to fully differential conversion.

The reference voltages are internally generated from an internal bandgap reference, with outside connection for decoupling purposes.

A power down capability is included for extremely low power dissipation in stand-by mode.

Silicon shows outstanding signal to noise ratio:


... and outstanding linearity:

This I&Q ADC is very suitable for any baseband front end in communication systems. It is optimized for low power applications requiring medium resolution and high-speed conversion rates, such as video, imaging, data acquisition, high-speed data reception and communications.


For SoC integration, Chipidea offers a wide range of Analog-Digital Interface Systems for Audio, Video, Multimedia, Data-Communications and Connectivity, including Power and Clock Management functions.