UCIe 32G IP
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UCIe Chiplet PHY & Controller
- Compliant with the UCIe specification (2.0 & 1.1)
- Flexible Structure, easy to customize (Pre-hardened PHY tuned to Customer Spec, PHY + Adapter Layer, PHY + Adapter Layer + Customized Protocol Layer)
- Supports the CXS/AXI using the streaming package (AXI Interface bandwidth up to 89%)
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D2D UCIe 1.1
- Compatible with UCIe v1.1 specification
- Features single-ended, source-synchronous, and DDR I/O signaling
- Supports 32-bit (16-bits TX + 16-bit RX) data bus per module for standard packages
- Offers a high clock frequency up to 16GHz
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UCIe based 8-bit 48-Gsps Transceiver (ADC/DAC/PLL/UCIe)
- 48-Gsps peak sample rate
- 8 bit resolution
- UCIe SP (16x lanes at 16Gbps) with streaming controller
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UCIe based 12-bit 12-Gsps Transceiver (ADC/DAC/PLL/UCIe)
- 12-Gsps peak sample rate
- 12 bit resolution (programmable)
- UCIe SP (16x lanes at 16Gbps) with streaming controller
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UCIe-S 64GT/s PHY IP
- The UCIe-S 64GT/s PHY IP is a cutting-edge solution designed to meet the growing demand for ultra-high-speed interconnects between dies in standard packaging environments.
- Leveraging the UCIe (Universal Chiplet Interconnect Express) 3.0 standard, this IP supports a blistering data rate of up to 64Gbps per lane, enabling next-generation AI, HPC, and data center SoC applications.
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UCIe-A 64GT/s PHY IP
- The UCIe-A 64GT/s PHY IP is a cutting-edge solution designed to meet the growing demand for ultra-high-speed interconnects between dies in advanced packaging environments.
- Leveraging the UCIe (Universal Chiplet Interconnect Express) 3.0 standard, this IP supports a blistering data rate of up to 64Gbps per lane, enabling next-generation AI, HPC, and data center SoC applications.