Ucie 32g IP

Compare 7 IP from 6 vendors (1 - 7)

UCIe PHY & D2D Adapter
- 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
- UCIe v1.1 specification
UCIe Chiplet PHY & Controller
- Compliant with the UCIe specification (2.0 & 1.1)
- Flexible Structure, easy to customize (Pre-hardened PHY tuned to Customer Spec, PHY + Adapter Layer, PHY + Adapter Layer + Customized Protocol Layer)
- Supports the CXS/AXI using the streaming package (AXI Interface bandwidth up to 89%)
Simulation VIP for UCIE
- Protocol Layer Features
- Streaming mode
- PCIe mode
- Protocol FDI LSMs
D2D UCIe 1.1
- Compatible with UCIe v1.1 specification
- Features single-ended, source-synchronous, and DDR I/O signaling
- Supports 32-bit (16-bits TX + 16-bit RX) data bus per module for standard packages
- Offers a high clock frequency up to 16GHz
UCIe based 8-bit 48-Gsps Transceiver (ADC/DAC/PLL/UCIe)
- 48-Gsps peak sample rate
- 8 bit resolution
- UCIe SP (16x lanes at 16Gbps) with streaming controller
UCIe based 12-bit 12-Gsps Transceiver (ADC/DAC/PLL/UCIe)
- 12-Gsps peak sample rate
- 12 bit resolution (programmable)
- UCIe SP (16x lanes at 16Gbps) with streaming controller
UCIe-S PHY and Controller
- Supports MCM, BGA packages and Chiplet2Chiplet interconnects on PCB
- Available process nodes: 28, 22, 16, 12, 7, 6nm
- X16 and X32 PHY with bump maps defined in UCIe 2.0 specifications
- Industry leading power consumption

UCIe 32G IP