Our silicon proven UCIE-S Interconnect IP Solutions, offer industry-leading power efficiency, performance, and low latency, tailored for the next generation of consumer electronics, automotive, high-performance computing, AI, and data center applications.
UCIe-S PHY and Controller
Overview
Key Features
- Supports MCM, BGA packages and Chiplet2Chiplet interconnects on PCB
- Available process nodes: 28, 22, 16, 12, 7, 6nm
- X16 and X32 PHY with bump maps defined in UCIe 2.0 specifications
- Industry leading power consumption
- Supports speeds: (Depends on channel insertion loss)
- Grand L: 4, 8, 12 and 16Gbps
- Grand H: 24 and 32Gbps
- Extreme low End-to-end Latency
- Patented voltage and Temperature Adaptive receiver to compensate voltage and temperature changes during transmission, result in zero or extreme low BER (Bit-Error-Rate)
- Real-time per lane data-eye monitor to monitor the health of each lane real time
- UCIe Controller supports all UCIe defined interfaces, AXI and CXS
Technical Specifications
TSMC
In Production:
5nm
Silicon Proven: 3nm , 4nm
Silicon Proven: 3nm , 4nm