The UCIe Chiplet IP offers a cutting-edge solution for seamless, low-latency data transfer between dies and chips, enabling heterogeneous integration for performance and efficiency gains. It supports die-to-die (D2D), chip-to-chip (C2C), interposer and PCB connectivity, ideal for data centers, 5G, HPC, and AI. The IP family includes UCIe-S (24Gbps/pin, 100um~150um pitch) for MCM/short PCB, and UCIe-A (32Gbps/pin, 25um~55um pitch) for silicon interposers. Both support scalable bandwidth (UCIe-A: 2048Gbps; UCIe-S: 384Gbps) with scalability for 1/2/4/8 modules and are compatible with UCIe standard and advanced package version.
UCIe Chiplet PHY & Controller
Overview
Key Features
- Compliant with the UCIe specification (2.0 & 1.1)
- Flexible Structure, easy to customize (Pre-hardened PHY tuned to Customer Spec, PHY + Adapter Layer, PHY + Adapter Layer + Customized Protocol Layer)
- Supports the CXS/AXI using the streaming package (AXI Interface bandwidth up to 89%)
- Supports the CXL/PCIE interface
- Fault Tolerance: Supports the CRC + Retry + FEC
- Supports FEC Mechanism (Optional)
- Low Power: Tunable Driver/Receiver Strength & auto clock gate (Clock Gate Ratio > 95%)
- Complete DFX mechanism for Debug
- Supports the Performance Monitor (bandwidth/latency monitor and event monitor)
- Supports the Complete BIST & On Die Scope mechanism (Covers protocol layer to the link layer)
- Supports the MCM, INFO, and Interposer package plus PCB
- High Performance: up to 24Gbps on MCM, 20Gbps on PCB, 32Gbps on interposer
- Auto Tracking: Forward Clock, Support PVT auto tracking
- Low Latency: Link layer latency to under 3ns
- Full training for the PHY Layer
- High Density: Standard Pitch and Micro Bump
Benefits
- Fully pre-assembled design, Drop-in hard macro to ease integration and speed time to market
- Zero risk with robust ESD architecture
- Extensive EDA tool support for various design and automation flow
- Optional CKE retention mode permits VDD and all non-essential I/Os to be powered down while retaining the external SDRAMs in self-refresh mode
- Comprehensive observation registers DFX and methods are available to facilitate customers in identifying issues during testing
Block Diagram
Deliverables
- Extensive documentation
- Models
- LIB
- LEF
- Place-and-route abstracts
- LVS netlist
- GDSII files