SR-IOV IP
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97
IP
from 13 vendors
(1
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10)
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SRIOV Verification IP
- Supports SRIOV specs 1.0/1.1.
- Supports PCIE Express specs 1.0/2.0/3.0/4.0/5.0.
- Supports PIPE, Serial, PCS/PMA, Low pin count and SerDes interface.
- Supports UVM and Verilog APIs supplied , as well as C DPI exports
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Verification IP for PCIe
- Accelerated confidence in simulation-based verification of RTL designs with PCI Express (PCIe) interfaces: PCIe Gen2/3/4/5/6/7
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Scalable Switch Intel® FPGA IP for PCI Express
- The Scalable Switch Intel® FPGA IP for PCI Express is a fully configurable switch that implements one fully configurable upstream port and connectivity for up to 64 downstream ports.
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R-Tile PCIe Hard IP
- R-Tile is a FPGA companion tile that supports configurations up to PCIe 5.0 x16 in Endpoint (EP), Root Port (RP), and Transaction Layer (TL) Bypass modes
- PCIe 3.0, 4.0, and 5.0 configurations are natively supported
- R-Tile also supports up to 16 SerDes channels through a PHY Interface for PCIe (PIPE) 5.1.1 in SerDes Architecture mode.
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P-Tile PCIe* Hard IP
- P-Tile is an FPGA companion tile available on Stratix® 10 DX and Agilex™ 7 FPGA F-Series device that natively supports PCIe* configurations up to 4.0 x16 in Endpoint (EP), Root Port (RP), and Transaction Layer (TL) Bypass Modes.
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L/H-Tile PCIe Hard IP
- Stratix® 10 FPGAs incorporate the L/H-Tile chiplets which include a configurable, hardened protocol stack for PCIe that is compliant with PCIe Base Specification 3.0
- This Avalon® Streaming Interface Hard IP supports PCIe 1.0, 2.0, and 3.0 data rates and x1, x2, x4, x8, or x16 configurations, including support for SR-IOV functionality.
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GTS PCIe Hard IP
- Agilex™ 5 FPGAs and SoC FPGAs are monolithic designs with integrated high-speed transceivers (GTS) and hardened PCIe controller IP supporting up to PCIe 4.0 x8 configurations for Root Port (RP), Endpoint (EP), and Transaction Layer (TL) bypass modes.
- GTS PCIe Hard IP for PCI Express Greatly Simplifies Design Integration for a Broad Range of Applications
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F-Tile PCIe Hard IP
- The F-Tile Intel® Hard IP supports PCIe* configurations up to 4.0 x16 in Endpoint (EP), Root Port (RP), and Transaction Layer (TL) Bypass Modes
- F-Tile serves as a companion tile for Agilex™ 7 devices.
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Intel® Arria® 10 and Intel® Cyclone® 10 PCIe Hard IP
- Intel® Arria® 10 and Intel® Cyclone® 10 GX FPGAs include a configurable, hardened protocol stack for PCI Express* that is compliant with the PCI Express Base Specification 3.0 and PCI Express Base Specification 2.0 respectively
- The hard IP provides the Avalon® Streaming (Avalon-ST) interface and can be configured for either Rootport (RP) or Endpoint (EP) modes.
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Multichannel DMA Intel FPGA IP for PCI Express*
- The Multichannel DMA IP for PCI Express provides high efficiency, speed, and configuration flexibility to support various applications from HPC, cloud, networking, to embedded
- With support for up to 2048 channels and Linux-based PCIe drivers provided, this low latency, low resource utilization solution is essential in handling movements of large volumes of data to optimize system performance.
