Agilex™ 5 FPGAs and SoC FPGAs are monolithic designs with integrated high-speed transceivers (GTS) and hardened PCIe controller IP supporting up to PCIe 4.0 x8 configurations for Root Port (RP), Endpoint (EP), and Transaction Layer (TL) bypass modes.
GTS PCIe Hard IP for PCI Express* Greatly Simplifies Design Integration for a Broad Range of Applications
- Hardened IP blocks reduce logic resourcing allowing for higher user logic integration
- Hardened IP blocks (complete protocol stack)
- Transaction Layer / Data Link Layer / PHY Layer (MAC), and PHY (PCS and PMA)
- SR-IOV (4 PFs, 256 VFs) enabling multiple applications on a single server - reducing Total Cost of Ownership (TCO)
- Faster timing closure decreases time-to-market design cycles
- Easy-to-use Design Tool Kit (DTK) for diagnostic and debug testing of PCIe design
