PCIe Controller

Overview

Compliant to PCI Express base specification 5.0

Key Features

  • Compliant to PCI Express base specification 5.0 (32 Gbps per lane) and backward compatible with PCI Express versions 4.0, 3.1, 2.0 and 1.1
  • Supports configurable number of PFs and VFs for SR-IOV
  • Architected for high link utilization and low latency
  • Efficient receive and transmit-retry buffering scheme
  • Completely handles PCI-Express ordering rules
  • Implements flow control logic in both directions
  • Supports PIPE 5.0 Compliant PHYs
  • Flexible lane ordering and support for lane reversal
  • Supports separate RefClk independent SSC architecture-SRIS
  • L1 PM Sub-states (Low Power States) with CLKREQ#
  • Supports Bifurcation
  • Support DM, RC, EP, SW

Technical Specifications

Short description
PCIe Controller
Vendor
Vendor Name
SMIC
Silicon Proven: 14nm
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Semiconductor IP