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Compare 1,282 IP from 98 vendors (1 - 10)
  • Scalable Switch Intel® FPGA IP for PCI Express
    • The Scalable Switch Intel® FPGA IP for PCI Express is a fully configurable switch that implements one fully configurable upstream port and connectivity for up to 64 downstream ports.
    Block Diagram -- Scalable Switch Intel® FPGA IP for PCI Express
  • Multichannel DMA Intel FPGA IP for PCI Express*
    • The Multichannel DMA IP for PCI Express provides high efficiency, speed, and configuration flexibility to support various applications from HPC, cloud, networking, to embedded
    • With support for up to 2048 channels and Linux-based PCIe drivers provided, this low latency, low resource utilization solution is essential in handling movements of large volumes of data to optimize system performance.
    Block Diagram -- Multichannel DMA Intel FPGA IP for PCI Express*
  • PCI v2.1 Host Controller
    • The PCI Host controller offers a PCI 32-bit bus operating at 33MHz and supports PCI devices conforming to the PCI Local Bus Specification 2.1.
    • PCI Host Bridge contains an internal arbiter to manage up to 4 external devices 
    Block Diagram -- PCI v2.1 Host Controller
  • PCI v2.1 Master/Slave controller
    • The PCI master/slave controller is fully compliant with PCI Local Bus Specification, Revision 2.3.
    • It has a fully customizable PCI Configuration Space. The controller supports both 32- and 64-bit PCI bus paths.
    • The application interface can be configured as a 32-bit bit as well as a 64-bit interface as per requirements.
    Block Diagram -- PCI v2.1 Master/Slave controller
  • PCI Express Verification IP
    • Supports PCI Express specs 1.0/2.0/2.1/3.0/4.0/5.0/6.0
    • Supports mPCIe
    • Supports PIPE, PCS/PMA, Message Bus and SERDES interface
    • Supports MPHY RMMI and serial interface
    Block Diagram -- PCI Express Verification IP
  • PCI Verification IP
    • Supports PCI specs 3.0.
    • Supports 32 and 64 bit addressing.
    • Supports 32 and 64 bit data
    • Supports back to back cycles
    Block Diagram -- PCI Verification IP
  • PCI Express Synthesizable Transactor
    • Supports PCI Express specs 1.0/2.0/3.0/4.0/5.0/6.0.
    • Supports MPCIE
    • Supports PIPE, PCS/PMA, and serdes interface
    • Supports MPHY RMMI and serial Interface
    Block Diagram -- PCI Express Synthesizable Transactor
  • PCI Synthesizable Transactor
    • Compliant to PCI 2.2/3.0 specifications
    • Supports 32/64 bit address and data
    • Supports arbiter which is 100% PCI spec compliant
    • Supports insertion of various types of errors
    Block Diagram -- PCI Synthesizable Transactor
  • PCI Master Slave IIP
    • Compliant with PCI version 2.0 Specification
    • Supports 32 bit address and data
    • Supports all types device select delays
    • Supports arbiter which is 100% PCI specification compliant
    Block Diagram -- PCI Master Slave IIP
  • PCI Express to AMBA 4 AXI/3 AXI Bridge
    • Complete IP solution consists of digital controllers, PHYs and verification IP
    • Fully supports the Synopsys Controller IP for PCI Express Endpoint, Root Port, Dual Mode (EP/RP), and Switch port types
    • Fully compliant with the AMBA 3 AXI and 4 AXI interconnects
    • Full protocol mapping from PCI Express to the AMBA 3 AXI or 4 AXI bus protocol
    Block Diagram -- PCI Express to AMBA 4 AXI/3 AXI Bridge
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