IP Catalog > Peripheral IP > Other > Multichannel DMA Intel FPGA IP for PCI Express*

Multichannel DMA Intel FPGA IP for PCI Express*

Overview

The Multichannel DMA IP for PCI Express provides high efficiency, speed, and configuration flexibility to support various applications from HPC, cloud, networking, to embedded. With support for up to 2048 channels and Linux-based PCIe drivers provided, this low latency, low resource utilization solution is essential in handling movements of large volumes of data to optimize system performance.

The Multichannel DMA IPs not only offer a variety of user logic interfaces as noted above, but in conjunction with our PCI-SIG* compliant PCI Express Hard IP, simplifies overall integration and speeds up design cycles.

The DMA is made up of channels that consist of Host to Device (H2D) and Device to Host (D2H) queue pairs. As shown in the figure, the Multichannel DMA can be used in a server’s hardware infrastructure to allow communication between various Virtual Machine (VM) based clients and their FPGA-device based counterparts. The DMA operates on descriptor-based queues set up by a Linux driver to transfer data between the FPGA and host. As the queues are filled, the control logic will read the queue descriptors and execute them. Once executed, the DMA will provide an interrupt to note completion of the transaction.

In building out PCI Express system-level solutions, the Multichannel DMA IP with the PCIe Hard IP both support Root Port (RP) and Endpoint (EP) topologies. This type of configuration compatibility and flexibility enables seamless integration into various platforms ranging from embedded to enterprise.

  •  
  •  

Key Features

  • Application interface options: AXI-Stream, Avalon Memory-Mapped, or Avalon Streaming
  • Agilex™ 7 FPGA DMA capabilities
    • Data Bus Width options: 256, 512, 1024
    • Support up to PCIe 5.0 x16
    •  Configurable up to 2048 channels
    • SR-IOV support (8 PFs, 2048 VFs)
  • Agilex™ 5 FPGA DMA capabilities
    • Data Bus Width options: 128, 256
    • Support up to PCIe 4.0 x8
    • Configurable up to 8 channels (up to 256 channels in future Quartus release)
    • SR-IOV support (1 PF, 8 VFs) (up to 4 PFs / 256 VFs in future Quartus release)
  • Root Port or Endpoint configurability
  • Integrated MSI-X interrupt for DMA operations
  • 10-bit tag support at the DMA level to ensure proper transaction tracking and management
  • Supports Completion reordering and Completion timeout
  • Architected to prevent head-of-line blocking across all channels

Block Diagram

Multichannel DMA Intel FPGA IP for PCI Express* Block Diagram

Technical Specifications

Short description
Multichannel DMA Intel FPGA IP for PCI Express*
Vendor
Vendor Name
Request Info

Related IPs

×
Semiconductor IP