PCI Synthesizable Transactor provides an smart way to verify the PCI component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's PCI Synthesizable Transactor is fully compliant with standard PCI Specification and provides the following features.
PCI Synthesizable Transactor
Overview
Key Features
- Compliant to PCI 2.2/3.0 specifications
- Supports 32/64 bit address and data
- Supports arbiter which is 100% PCI spec compliant
- Supports insertion of various types of errors
- Supports insertion of delays in both master and slave
- Supports all types devsel delays
- Supports data bursting for back to back access
- Master is capable of generating all types of PCI transactions
- Slave is capable of responding to all types of PCI transactions
- Slave supports INTA/B/C/D
- Supports multi master and multi slave instances for creating complex PCI sub system
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
Block Diagram
Deliverables
- Synthesizable transactors
- Complete regression suite containing all the PCI testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation contains User's Guide and Release notes