PCI Verification IP

Overview

PCI Verification IP provides an smart way to verify the PCI bi-directional bus. The SmartDV's PCI Verification IP is fully compliant with version 3.0 of the PCI Specification and provides the following features.

PCI Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

PCI Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports PCI specs 3.0.
Supports 32 and 64 bit addressing.
Supports 32 and 64 bit data
Supports back to back cycles
Supports arbiter which is 100% PCI spec compliant
Supports all types of wait states insertion
Supports insertion of delays in both master and slave
Supports all types devsel delays
Provides error injection with a wide variety of error types
Supports data bursting for back to back access
Complex verification environment
Master is capable of generating all types of PCI transactions
Slave is capable of responding to all types of PCI transactions
Slave supports INTA/B/C/D
Callbacks in Master, Slave and monitor for user processing of data.
Supports multi master and multi slave instances for creating complex PCI sub system.
Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
PCI Verification IP comes with complete testsuite to test every feature of PCI specification.
Supports scoreboard checking
Built-in monitors for protocol checking, including a global bus monitor.
Functional coverage to cover all functionality of PCI Master and End Slave
Support for multiple instantiations to create complex verification environment.

Benefits

Faster testbench development and more complete verification of PCI designs.
Easy to use command interface simplifies testbench control and configuration of Master and Slave
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the PCI testcases to certify PCI Master and Slave.
Examples showing how to connect various components, and usage of BFM and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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