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MIPI M-PHY 4.1 IP

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Compare 15 IP from 6 vendors (1 - 10)
  • MIPI 4.1 M-PHY HS Gear 4
    • Supports high speed data transfer G4A/B and backward compatible
    • Multi-lane compatible
    • Supports 4 reference clocks as per MIPI 4.1 specification
    Block Diagram -- MIPI 4.1 M-PHY HS Gear 4
  • Simulation VIP for MIPI M-PHY
    • Specification Compliance
    • Complies with MIPI M-PHY 4.0, 4.1 and 5.0 specification
    • M-PHY Type 1 and Type 2
    • Supports Type 1 and Type 2
    Block Diagram -- Simulation VIP for MIPI M-PHY
  • MIPI MPHY Verification IP
    • Supports 3.0,4.1 and 5.0 MIPI MPHY Specification.
    • Support Type-1 and Type-II operations.
    • Supports both serial and protocol layer interface.
    • Supports all PWM 0-7 gear of operation.
    Block Diagram -- MIPI MPHY Verification IP
  • MIPI M-PHY HS-G4 IP (M-PHY v4.1) in TSMC 40G
    • Supports MIPI® Alliance Specification for M- PHY® Version 4.1.
    • Dual-simplex point-to-point interface with ultra-low voltage differential signaling.
    • Slew-rate control for EMI reduction.
    Block Diagram -- MIPI M-PHY HS-G4 IP (M-PHY v4.1) in TSMC 40G
  • UFS 3.1 Host Controller compatible with M-PHY 4.1 and UniPro 1.8
    • Seamless integration from PHY to Software
    • Assured compliance across all components
    • Single point of support
    Block Diagram -- UFS 3.1 Host Controller compatible with M-PHY 4.1 and UniPro 1.8
  • MIPI M-PHY v4.1 IP, Silicon Proven in UMC 28 HPC
    • Compliant with M-PHY Spec 4.1, UniPro Spec 1.8, UFS Spec 3.0
    • Support HS-MODE Gear4(A/B) with data rate up to 11.6Gb/s, and backward compatible
    Block Diagram -- MIPI M-PHY v4.1 IP, Silicon Proven in UMC 28 HPC
  • MIPI M-PHY v3.1 IP, Silicon Proven in UMC 40LP
    • Compliant with M-PHY Spec 4.1, UniPro Spec 1.8, UFS Spec 3.0
    • Support HS-MODE Gear4(A/B) with data rate up to 11.6Gb/s, and backward compatible
    • Support LS-MODE PWM-G1 to PWM-G5 with data rate up to 144Mb/s
    • Support reference clock frequency with 19.2/26/38.4/52MHz defined in UFS spec.
    Block Diagram -- MIPI M-PHY v3.1 IP, Silicon Proven in UMC 40LP
  • MIPI M-PHY v4.1 IP, Silicon Proven in TSMC 12FFC
    • Compliant with M-PHY Spec 4.1, UniPro Spec 1.8, UFS Spec 3.0
    • Support HS-MODE Gear4(A/B) with data rate up to 11.6Gb/s, and backward compatible
    • Support LS-MODE PWM-G1 to PWM-G5 with data rate up to 144Mb/s
    • Support reference clock frequency with 19.2/26/38.4/52MHz defined in UFS spec.
    Block Diagram -- MIPI M-PHY v4.1 IP, Silicon Proven in TSMC 12FFC
  • MIPI M-PHY G4 Designed For TSMC 28nm HPC+
    • Compliant to MIPI Alliance Standard for M-PHY specification Version 4.1
    • Supports M-PHY Type-I system
    • Support for Clock and Data Recovery Options
    Block Diagram -- MIPI M-PHY G4 Designed For TSMC 28nm HPC+
  • MIPI UniPro Verification IP
    • Supports MIPI UniPro specification 1.41,1.6,1.8 and 2.0.
    • Support MIPI MPHY specification 3.0,4.1 and 5.0.
    • Supports data control at each layer of UniPro Specification for easy debug.
    • Supports multiple connections in L4 Layer and L4 segments.
    Block Diagram -- MIPI UniPro Verification IP
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