MIPI M-PHY v3.1 IP, Silicon Proven in UMC 40LP

Overview

The most recent MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-PHY v3.0 Specification, UniPro v1.8 Specification, and Universal Flash Storage (UFS) v3.0 Specification are all supported by the MIPI M-PHY Gear 3 IP. a high-bandwidth serial interface technology that can support HS Gear3 rates of up to 5.8Gbps and was specifically created for mobile applications to achieve reduced pin count and excellent battery efficiency. The UniPro controller and UFS Controller are supported by the RMMI interface-compliant MIPI M-PHY Gear 3 IP. The MIPI M-PHY offers reliable embedded system debugging and receiver ocular data monitoring using low-cost Build-In-Self-Test (BIST).

Key Features

Compliant with M-PHY Spec 4.1, UniPro Spec 1.8, UFS Spec 3.0
Support HS-MODE Gear4(A/B) with data rate up to 11.6Gb/s, and backward compatible
Support LS-MODE PWM-G1 to PWM-G5 with data rate up to 144Mb/s
Support reference clock frequency with 19.2/26/38.4/52MHz defined in UFS spec.
Support RMMI interface for Type-I application
Receiver eye open for monitoring and debugging
Support Build-In-Self Test(BIST) for low-cost CP/FT
Silicon Proven in UMC 40LP

Benefits

2-tap DFE, CTLE, 2-tap FFE
Channel Loss: >14dB @6GHz Nyquist
Low HS-Gear4 operation current and low standby current
Competitive IP PPA leading in the market

Block Diagram

Deliverables

Application Note / User Manual
Behaviour model, and protected RTL codes
Protected Post layout netlist and Standard Delay Format (SDF)
Library (LIB)
Frame view (LEF)
Metal GDS (GDSII)
Test patterns and Test Documentation

Technical Specifications

Foundry, Node

UMC 40LP

Maturity

In Production

Availability

Immediate

UMC

In Production: 40nm LP

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