MIPI M-PHY v4.1 IP, Silicon Proven in UMC 28 HPC
Overview
The MIPI M-PHY Gear 4 IP is compatible with the most recent MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-PHY v4.1 Specification, UniPro v1.8 Specification, and Universal Flash Storage (UFS) v3.0 Specification. a high-bandwidth serial interface technology that was created especially for mobile applications to achieve decreased pin count and superior energy efficiency. It can support HS Gear4 rates of up to 11.6Gbps. The RMMI interface-compatible MIPI M-PHY Gear 4 IP supports the UniPro controller and UFS Controller. The MIPI M-PHY provides a low-cost Build-In-Self-Test for dependable embedded system debugging and receiver ocular data monitoring (BIST).
Key Features
- Compliant with M-PHY Spec 4.1, UniPro Spec 1.8, UFS Spec 3.0
- Support HS-MODE Gear4(A/B) with data rate up to 11.6Gb/s, and backward compatible
- Support LS-MODE PWM-G1 to PWM-G5 with data rate up to 144Mb/s
- Support reference clock frequency with 19.2/26/38.4/52MHz defined in UFS spec.
- Support RMMI interface for Type-I application
- Receiver eye open for monitoring and debugging
- Support Build-In-Self Test(BIST) for low-cost CP/FT
- Silicon Proven in UMC 28HPC+
Benefits
- RX:DFE+CTLE, TX:2-tap FFE
- Max. Channel Loss:~14dB @6GHz Nyquist
- Low operation current and low standby current
- Competitive IP PPA leading in the market
Block Diagram
Deliverables
- Application Note / User Manual
- Behaviour model, and protected RTL codes
- Protected Post layout netlist and Standard Delay Format (SDF)
- Library (LIB)
- Frame view (LEF)
- Metal GDS (GDSII)
- Test patterns and Test Documentation
Technical Specifications
Short description
MIPI M-PHY v4.1 IP, Silicon Proven in UMC 28 HPC
Vendor
Vendor Name
Foundry, Node
UMC 28HPC+
Maturity
In Production
Availability
Immediate
UMC
Silicon Proven:
28nm
HPC
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