MIPI UniPro Verification IP

Overview

Key Features

• Supports MIPI UniPro specification 1.41,1.6,1.8 and 2.0.
• Support MIPI MPHY specification 3.0,4.1 and 5.0.
• Supports data control at each layer of UniPro Specification for easy debug.
• Supports multiple connections in L4 Layer and L4 segments.
• Support all valid segment sizes in L4 Layer.
• Supports invalid field value insertion and detection in L4 Layer.
• Supports end to end flow control at L4 layer.
• Supports Cport arbitration at both segment level and packet level.
• Supports Layer 3 error injection and detection.
• Supports L2 data frames and control frames.
• Supports injection of Errors and detection of errors in L2 data frames and control frame to test all cases as per specs.
• Support preemption and preemption error injection for L2 data frames.
• Phy layer supports MPHY serial, MPHY RMMI (10,20,40,80 and 160 bit) Interface.
• Phy layer supports multi lanes, Type-I and all power modes for Mphy.
• Supports all types lane mapping (Lane 0 mapped to 1,2,3 etc).
• Support error injection of all PACP frames.
• Periodic deskew pattern injection, filler injections supported.
• Supports link startup as per specs.
• Supports Qos monitoring features
• Various types of error injection during LSS supported.
• Various types of errors in PACP request and responses frames.
• Supports CPort buffer based E2E checking.
• Supports Scrambler, Skip pattern insertion as per specs.
• Supports Lane to Lane skew feature in Serial & RMMI Interface
• Support fine grain control and when flow control needs to be done and how to respond to flow control.
• Unipro MPHY layer in HS mode supports clock recovery.
• Supports callbacks for user to get packets or errors in transmitter and receiver and monitor.
• MIPI UniPro verification IP comes with complete testsuite to test every feature of MIPI UniPro spec.
• Functional coverage for each functional condition in env.
• Notifies the testbench of significant events such as transactions, warnings, timing and protocols violations.
• Supports independent communication in forward and reverse direction simultaneously.
• Supports M-PHY physical layer support with RMMI or serial support.
• Supports up to four M-PHY lanes.
• Supports Scrambler, SKIP insertion and Marker 2 extension.
• Supports Lane to Lane skew feature in Serial Interface
• Supports both data link layer frames,
• Data frames.
• Control Frames.
• PHY layer features,
• Transmission and reception of encoded PHY symbols.
• Transmission of PHY IDLE symbols when no data is supplied.
• Detection of PHY IDLE symbols.
• Method to re-initialize the forward Link to overcome error situations.
• Provision of different power modes and a method to signal them from transmitter to receiver.
• Supports clock recovery.
• PHY adapter layer features,
• Transmission and reception of Data Link layer control symbols and data symbols via underlying PHY.
• Lane distribution and merging in multi-lane ports.
• Provision of MIPI UniPro power management operating modes.
• (Re-)Initialization of the PHY TX path.
• Support transmit lane connect/disconnected features.
• Supports one lane mapping to different lanes.
• Support various kind of errors injects in LSS, PA Layer for various operation.
• Support PHY testing [Test mode feature]
• Data Link layer features,
• Frame composition.
• Frame decomposition.
• Buffering Mechanism.
• Supports frame preemption.
• Triggering of PHY initialization.
• Supports fine grain testing of flow control.
• Support for two traffic classes by priority-based arbitration.
• Support various preemption error injections.
• Supports creating all cases of error injection for L2 layer.
• Error injection in PA_init process.
• Detect various protocol errors.
• Network layer features,
• Packet composition and packet decomposition.
• Packet format recognition.
• Support for traffic Class.
• Error handling.
• Transport layer features,
• Segmentation and Reassembly.
• Segment Composition and Segment Decomposition.
• Segment format recognition.
• Connections management.
• End-to-End flow-control.
• Error handling.
• Different CPort arbitration algorithms supported.
• Support L4 Test Feature
• Various kinds of error injection,
• Various kinds of error detection.
• Cport Buffer management to mimic real life cases.
• Supports complete DME functionality,
• Supports all layer error injection and detection.
• Supports various kind of TX and RX errors generation and detection on M-PHY,
• Disparity errors.
• Invalid control chars.
• Invalid sync sequencer errors.
• Timeout conditions injections.
• CRC errros.
• Monitor, Detects and notifies the testbench of all protocol and timing errors.
• Supports constraints Randomization.
• Status counters for various events in bus.
• Callbacks in transmitter and receiver for various events.
• Supported below latest Unipro Version 2.0 features
• Supports HS-G5 gear in HS mode and PWM G1 gear alone supported, remaining PWM gears are removed
• Supports Linkstartup sequence start either HS Mode(HS G1A or HS G1B) or LS mode(PWM G1)
• Supports L2 buffer extension
• Supports PA capability user data in PACP CAP IND frame
• Save config time is extended by using extended save time attributes. Additionally included with save time
• Supports RMMI bus width extended to 80bits and 160 bits per lane interface in PHY Layer

Benefits

• Faster testbench development and more complete verification of MIPI UniPro designs.
• Easy to use command interface simplifies testbench control and configuration of Tx,Rx and monitor
• Simplifies results analysis.
• Runs in every major simulation environment.

Block Diagram



Deliverables

• Complete regression suite containing all the MIPI UniPro testcases.
• Examples showing how to connect various components, and usage of Tx,Rx and Monitor.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation also contains User's Guide and Release notes.

Technical Specifications