MCU IP
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156
IP
from 49 vendors
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10)
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High-perf embedded MCU processor
- RV64IMCAFD ISA
- Dual-issue in-order
- SMP 1-4 cores per cluster
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Root of Trust - Foundational security for SoCs, secure MCU devices and sensors
- Secure Boot assist to host CPU(s) and protection of key material
- Secure firmware upgrade management for Host CPU
- Lifecycle management support
- Secure Debug support
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MCU core with high-performance FPU (32 or 64 bit)
- Harvard architecture (separate instruction and data buses)
- RV32IMCF[DA] or RV64IMCF[DA] ISA
- User and Machine privilege modes
- High-performance IEEE 754-2008 compliant floating-point unit
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Compact 32-bit MCU core for deeply embedded applications and accelerator control
- 32bit microcontroller core with RISC-V ISA
- Harvard architecture, separate Instruction and Data memories
- 32 or 16 32bit integer registers
- RV32I or E basic instruction set, optional M and C extensions
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MCU PAD - SMIC 55nm Eflash
- 5V/1.8V/3.3V/1.2V power supply can be used, not only compatible with normal 1.8V/3.3V
- powering system, and also 5V or lithium battery powering system
- ? Including ultra-low leakage MCU I/O total solution
- ? Supports 1.2V core voltage power off, and get ultra-low leakage
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MCU PAD - SMIC 55nm Eflash
- 1.8V/3.3V/1.2V power supply can be used
- ? Including ultra-low leakage MCU I/O total solution
- ? Supports 1.2V core voltage power off, and get ultra-low leakage
- ? Provides a wide variety of interrupt I/O for customers to easily communicate with outside
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8-bit MCU
- FAST architecture, 4 times faster than the original implementation
- Software compatible with industry standard 68HC11
- 10 times faster multiplication
- 16 times faster division
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Low Power MCU I/O
- Supports digital core voltage power off, and get ultra-low leakage
- All GPIOs support that the voltage of PAD is higher than I/O power
- DUP structure to help customer reduce cost
- Built in power-on-control function to prevent chip latch-up potential risk during chip
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S51 Low-power 64-bit MCU RISC V core
- Fully compliant with the RISC-V ISA specification
- RV64IMAC Support
- RV64I - 64-bit RISC-V with 32 integer registers
- Integer Multiplication and Division (M) support
