S51 Low-power 64-bit MCU RISC V core

Overview

The SiFive S51 Standard Core is a 64-bit embedded processor, fully compliant with the RISC-V ISA. A small-footprint, low-power design makes the S51 ideal for devices that require a tiny system controller in a larger 64-bit SoC. The S51 can also be used as a standalone controller for networking, storage, or other high-performance embedded applications

Key Features

Fully compliant with the RISC-V ISA specification
RV64IMAC Support
RV64I - 64-bit RISC-V with 32 integer registers
Integer Multiplication and Division (M) support
Atomic Mode (A) support for high-performance, portable software
Compressed Mode (C) support for better code density
Machine and User Mode Support
In-order, 5-6 stage variable pipeline
Advanced Memory Subsystem
16KB, 2-way Instruction Cache
Instruction Tightly Integrated Memory (ITIM) option
Up to 64KB Data Tightly Integrated Memory (DTIM) support
Support for up to 40 physical address bits
Efficient and Flexible Interrupts
Local interrupts w/ vectored addresses - up to 16
Platform Level Interrupt Controller (PLIC) - 511 interrupts w/ 7 priority levels
RISC-V Core Local Interruptor (CLINT) - 1 timer, 1 SW
8-Region Physical Memory Protection (PMP)
High performance AMBA or TileLink Interface
2.87/1.7 DMIPS/MHz (Best Effort/Legal)
3.01 CoreMark/MHz

Block Diagram

Deliverables

RTL Evaluation
Test Bench RTL
Software Development Kit
FPGA Bitstream
Documentation

Technical Specifications

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