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LPDDR3 IP

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Compare 155 IP from 14 vendors (1 - 10)
  • LPDDR3 IP solution
    • Compatible with LPDDR3 up to 2133Mbps
    • AXI compliant multi-ports, and data width, FIFO depth, command queue depth configurable
    • DFI compliant interface between controller and PHY
    • Support ECC (error correcting code)
    Block Diagram -- LPDDR3 IP solution
  • LPDDR3 Synthesizable Transactor
    • Supports 100% of LPDDR3 protocol standard JESD209-3, JESD209-3B and JESD209-3C
    • Supports all the LPDDR3 commands as per the specs
    • Supports up to 32GB device density
    • Supports the following devices:
    Block Diagram -- LPDDR3 Synthesizable Transactor
  • LPDDR3 DFI Synthesizable Transactor
    • Compliant with DFI version 3.1 or higher Specifications.
    • Supports LPDDR3 devices compliant with JEDEC LPDDR3 SDRAM Standard JESD209-3.pdf, JESD209-3B.pdf and JESD209-3C.pdf
    • Supports for Read data-eye training.
    • Supports for Read gate training.
    Block Diagram -- LPDDR3 DFI Synthesizable Transactor
  • LPDDR3 Memory Model
    • Supports LPDDR3 memory devices from all leading vendors.
    • Supports 100% of LPDDR3 protocol standard JESD209-3, JESD209-3B and JESD209-3C.
    • Supports all the LPDDR3 commands as per the specs.
    • Supports up to 32GB device density
    Block Diagram -- LPDDR3 Memory Model
  • LPDDR3 DFI Verification IP
    • Compliant with DFI version 3.1 or higher Specifications.
    • Supports LPDDR3 devices compliant with JEDEC LPDDR3 SDRAM Standard JESD209-3.pdf, JESD209-3B.pdf and JESD209-3C.pdf
    • Supports for Read data-eye training
    • Supports for Read gate training
    Block Diagram -- LPDDR3 DFI Verification IP
  • LPDDR3 Controller IIP
    • Supports 100% of LPDDR3 protocol standard JESD209-3, JESD209-3B and JESD209-3C.
    • Compliant with DFI version 3.1 or higher Specification.
    • Supports all the LPDDR3 commands as per the specs.
    • Supports up to 16 AXI ports with data width upto 512 bits.
    Block Diagram -- LPDDR3 Controller IIP
  • LPDDR3 Assertion IP
    • Specification Compliance
    • Supports all signal level checks including X detection
    • Support for check-points include power on, Initialization and power off rules,
    • Support for state based rules, Active Command rules,
    Block Diagram -- LPDDR3 Assertion IP
  • LPDDR3 DFI Assertion IP
    • Specification Compliance
    • Compliant with DFI version 3.1 or higher Specifications.
    • Supports LPDDR3 devices compliant with JEDEC LPDDR3 SDRAM Standard JESD209-3.pdf, JESD209-3B.pdf and JESD209-3C.pdf.
    • Supports for Read data-eye training.
    Block Diagram -- LPDDR3 DFI Assertion IP
  • Performance Enhanced version of uMCTL2 supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3 and LPDDR2 for Automotive
    • Select a complete multi-ported Enhanced Universal DDR Memory Controller offering 1 to 16 host ports, or join a third-party scheduler to a single-port Enhanced Universal Protocol Controller
    • Support for JEDEC standard DDR2, DDR3, DDR4, LPDDR/Mobile DDR, LPDDR2, LPDDR3, and LPDDR4 SDRAMs
    • Compatible with all Synopsys DDR PHYs (excluding DDR2/DDR PHYs) using DFI-compliant interfaces
    Block Diagram -- Performance Enhanced version of uMCTL2 supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3 and LPDDR2 for Automotive
  • Performance Enhanced version of DDR Enhanced Memory Ctl (uMCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2
    • Select a complete multi-ported Enhanced Universal DDR Memory Controller offering 1 to 16 host ports, or join a third-party scheduler to a single-port Enhanced Universal Protocol Controller
    • Support for JEDEC standard DDR2, DDR3, DDR4, LPDDR/Mobile DDR, LPDDR2, LPDDR3, and LPDDR4 SDRAMs
    • Compatible with all Synopsys DDR PHYs (excluding DDR2/DDR PHYs) using DFI-compliant interfaces
    Block Diagram -- Performance Enhanced version of DDR Enhanced Memory Ctl (uMCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2
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