LPDDR3 Memory Model

Overview

LPDDR3 Memory Model provides an smart way to verify the LPDDR3 component of a SOC or a ASIC. The SmartDV's LPDDR3 memory model is fully compliant with standard LPDDR3 Specification and provides the following features. Better than Denali Memory Models.

LPDDR3 Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

LPDDR3 Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports LPDDR3 memory devices from all leading vendors.
Supports 100% of LPDDR3 protocol standard JESD209-3, JESD209-3B and JESD209-3C.
Supports all the LPDDR3 commands as per the specs.
Supports up to 32GB device density
Supports the following devices.

Supports all data rates as per specification.
Quickly validates the implementation of the LPDDR3 standard JESD209-3, JESD209-3B and JESD209-3C.
Supports for Programmable READ/WRITE Latency timings.
Supports for Burst sequence.
Checks for following

Check-points include power up, initialization and power off rules,
State based rules, Active Command rules,
Read/Write Command rules etc.
All timing violations.

Supports for All Mode register programming.
Supports for write data mask and data strobe features.
Supports for Power Down features.
Supports for Deep Power Down features.
Supports for input clock stop and frequency change.
Supports for Write leveling.
Supports for ZQ calibration.
Supports for CA training and DQ calibration.
Supports for ODT (On-Die Termination features).
Supports for full-timing as well as behavioral versions in one model.
Supports for all timing delay ranges in one model: min, typical and max.
Constantly monitors LPDDR3 behavior during simulation.
Protocol checker fully compliant with LPDDR3 Specification JESD209-3, JESD209-3B and JESD209-3C.
Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
Built in functional coverage analysis.
Supports Callbacks, so that user can access the data observed by monitor

Benefits

Faster testbench development and more complete verification of LPDDR3 designs.
Easy to use command interface simplifies monitor control and configuration.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the LPDDR3 testcases.
Complete UVM/OVM sequence library for LPDDR3 controller.
Examples showing how to connect and usage of Model.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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