IP Catalog > Interface IP > Memory Interface IP > LPDDR IP > LPDDR3 IP > LPDDR3 Controller IP > LPDDR3 DFI Assertion IP

LPDDR3 DFI Assertion IP

Overview

DFI LPDDR3 Assertion IP provides an smart way to verify the ARM DFI LPDDR3 component of a SOC or a ASIC. The SmartDV's DFI LPDDR3 Assertion IP is fully compliant with standard DFI LPDDR3 Specification and provides the following features.

LPDDR3 DFI Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

LPDDR3 DFI Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Specification Compliance
    • Compliant with DFI version 3.1 or higher Specifications.
    • Supports LPDDR3 devices compliant with JEDEC LPDDR3 SDRAM Standard JESD209-3.pdf, JESD209-3B.pdf and JESD209-3C.pdf.
    • Supports for Read data-eye training.
    • Supports for Read gate training.
    • Supports for Write date-eye training.
    • Supports for CA training.
    • Supports for DFI disconnect during training.
    • Supports for write data mask and data strobe features.
    • Supports for Power Down features.
    • Supports for Deep Power Down features.
    • Supports all data rates as per specification.
    • Supports for Burst sequence.
    • Supports for input clock stop and frequency change.
    • Supports for Write leveling.
    • Supports for X16 and X32 mode.
    • Supports DRAM Clock disabling feature.
    • Supports Error signaling.
    • Supports Independent Operation & Multi-Configuration Support for LPDDR3.
    • Supports all types of timing and protocol violations detection for timing parameters.
    • Constantly monitors DFI behavior during simulation.
    • Protocol checker fully compliant with DFI 3.1 or higher Specifications.
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV DFI LPDDR3 VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure DFI LPDDR3 Assertion IP functionality.

Benefits

  • Runs in every major formal and simulation environment.

Block Diagram

LPDDR3 DFI Assertion IP Block Diagram

Deliverables

  • Detailed documentation of Assertion IP usage.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

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