LPDDR3 Synthesizable Transactor provides a smart way to verify the LPDDR3 component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's LPDDR3 Synthesizable Transactor is fully compliant with standard LPDDR3 Specification and provides the following features.
LPDDR3 Synthesizable Transactor
Overview
Key Features
- Supports 100% of LPDDR3 protocol standard JESD209-3, JESD209-3B and JESD209-3C
- Supports all the LPDDR3 commands as per the specs
- Supports up to 32GB device density
- Supports the following devices:
- X16
- X32
- Supports all data rates as per specification
- Supports programmable read/write latency timings
- Supports burst sequence
- Checks for following:
- Check-points include power up, initialization and power off rules
- State based rules, active command rules
- Read/write command rules etc
- All timing violations
- Supports all mode register programming
- Supports write data mask and data strobe features
- Supports power down features
- Supports deep power down features
- Supports write leveling
- Supports ZQ calibration
- Supports CA training and DQ calibration
- Supports ODT (on-die termination features)
- Supports full-timing as well as behavioral versions in one model
- Protocol checker fully compliant with LPDDR3 specification JESD209-3,JESD209-3B and JESD209-3C
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
Block Diagram
Deliverables
- Synthesiable transactors
- Complete regression suite containing all the LPDDR3 testcases
- Example's showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation also contains User's Guide and Release notes