IP Catalog > Interface IP > Memory Interface IP > LPDDR IP > LPDDR3 IP > LPDDR3 Controller IP > LPDDR3 Assertion IP

LPDDR3 Assertion IP

Overview

LPDDR3 Assertion IP provides an efficient and smart way to verify the LPDDR3 designs quickly without a testbench. The SmartDV's LPDDR3 Assertion IP is fully compliant with standard LPDDR3 Specification.

LPDDR3 Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

LPDDR3 Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Specification Compliance
    • Supports all signal level checks including X detection
    • Support for check-points include power on, Initialization and power off rules,
    • Support for state based rules, Active Command rules,
    • Support for Read/Write Command rules etc.
    • Support for all timing violations.
    • Supports all legal data and address widths configuration
    • Supports different Read/write latency
    • Supports power down and deep power down
    • Supports clock stop feature
    • Supports mode register command period configurability
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV LPDDR3 VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure LPDDR3 Assertion IP functionality.

Benefits

  • Runs in every major formal and simulation environment.

Block Diagram

LPDDR3 Assertion IP Block Diagram

Deliverables

  • Detailed documentation of Assertion IP usage.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

Request Info

Related IPs

×
Semiconductor IP