Ensilica IP

• Throughput of greater than 8Gsps with 1GHz core clock frequency
• Architecture can be scaled to support higher throughput per clock cycle
• Configurable to supports large transform sizes i.e >8k

• 1 clock cycle per point, no gap required between packets
• Run-time selection of any power of 2 FFT points
• Run-time selection of froward or inverse transform

• 1 clock cycle per point, no gap required between packets
• Run-time selection of any power of 2 FFT points
• Run-time selection of forward or inverse transform
• Internal convergent rounding

• Real or Complex valued IFFT/FFT options
• Per transform selection of FFT size from 8 to 32768 points
• Per transform selection of FFT or IFFT
• Efficient mixed radix 4/2 dragonfly for low cycle count

• Designed to accelerate post-quantum Key Encapsulation Mechanism (KEM) as defined by NIST FIPS 203.

Hardware core for accelerating the high-level operations specified in the NIST FIPS 204 standard.

• Supports variable length SHA-3 Hash Functions
• Supports Extendable Output Functions (XOF)
• Configurable architecture for achieving the required performance and silicon area

• Ka-Band operation: Rx 17.7 to 21.2 GHz, Tx 27.5 to 30 GHz
• Ka-Band fine gain control in each Rx/Tx element

• ASIC or FPGA target
• Generates 256 random bits at a time
• Multiple ring oscillators with post processing for true random bit generation
• Fully compliant with latest NIST 800-22 800-22 and Diehard Random test suite

• Two Channels of multi-lead electrocardiogram (ECG)
• Temperature sensor
• Differential capacitive sensor channel