Post Quantum ready Public Key Crypto HW acceleration library optimized for networking applications

Overview

eSi-PQC-HT is a post quantum ready Public Key Crypto HW acceleration library, optimized for networking applications.

eSi-PQC-HT supports the following cryprographic functions in a fully hardware architecture:
* ML-KEM KeyGen, Encaps, Decaps operations for all security modes in FIPS 203;
* ML-DSA Keygen, Sign, Verify operations for all security modes in FIPS 204;
* ECDSA Sign/Verify operations for all NIST prime field curves;
* ECC public key generation for all NIST prime field standardized curves;
* SHA3/SHAKE operations specified in FIPS 202;

The full hardware architecture is optimized for wired/wireless networking applications demanding high throughputs and low processing latency. It also makes the IP compatible with both SoC and simpler non-SoC chip architectures.

Key Features

  • ML-KEM (FIPS 203)
    • ML-KEM.KeyGen/Encaps/Decaps
    • ML-KEM-512/768/1024
    • Constant time operations for resistance against time analysis attacks
    • Configurable arithmetic unit architecture for achieving the required performance and silicon area
    • Operation times ~10us for ML-KEM-1024 at 1GHz
  • ML-DSA (FIPS 204):
    • ML-DSA.KeyGen/Sign/Verify
    • ML-DSA-44/65/87
    • Constant time operations for resistance against time analysis attacks
    • Configurable arithmetic unit architecture for achieving the required performance and silicon area
    • Processing times for KeyGen/Verify ~20us at 1GHz
    • Average processing time for Sign ~120us at 1GHz
  • ECDSA/ECC (FIPS 186-5)
    • ECDSA.Sign/Verify
    • ECC.PubKeyGen
    • Constant time operations for resistance against time analysis attacks
    • Configurable arithmetic unit architecture for achieving the required performance and silicon area
    • Operation times ~1ms for P-521 at 1GHz
  • SHA3/SHAKE (FIPS 202)
    • SHA3-224/256/384/512
    • SHAKE-128/256
    • 64-bit AXI Stream interface
    • Double data buffering for loading/unloading data while core is busy
    • 24 clock cycles per Keccak round

Applications

  • Datacentres / Cloud computing
  • Wired and wireless networking
  • Edge AI computing

Deliverables

  • Verilog RTL
  • C Model
  • Testbench
  • Software libraries

Technical Specifications

Foundry, Node
Any
Availability
Now
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Semiconductor IP