High performance FFT optimised for Radar

Overview

A configurable highly efficient pipelined radix-2 squared FFT with additional functionality making it optimised for point cloud generation in Radar. Ported to both ASIC and FPGA technology and achieving a very high clock speed with minimal logic and memory.

EnSilica has a comprehensive range of FFT IP cores, these cores can be configured to replace the AMD FFT LogiCORE™ IP or FFT Intel® FPGA IP Core when migrating an FPGA design to ASIC technology.

Key Features

1 clock cycle per point, no gap required between packets
Run-time selection of any power of 2 FFT points
Run-time selection of froward or inverse transform
Multichannel data windowing
Multichannel real and complex input pipelined FFT(using Muti-channel FFT )
Optional path loss compensation
Optional FFT reordering to natural or centre shifted
Optional Array phase and amplitude alignment
Optional PSD accumulation module
Optional Log2 and decibel calculation module
Optional control unit for cycling over 4D FFT
Optional 4D hypersphere clustering
Optional 2:1 and 4:1 IQ data point compression/decompression
AXI4 streaming interface

Benefits

Run time selection of transform size
Optimised featured for use in Radar
Silicon proven in ISO-26262 certified products
Common code for FPGA and ASIC simplifies prototyping
Can be parameterized for exact requirements
Delivered with memories ported to your technology node

Applications

Advanced automotive Radar systems
4D Radar
LiDAR and Radar point cloud generation

Deliverables

RTL
Testbench
Synthesis scripts
Documentation
MATLAB and C++ bit exact model
CUDA accelerated bit exact model

Technical Specifications

Maturity

Silicon proven

Availability

Available Now

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