array:1 [
"searches" => array:3 [
0 => array:11 [
"q" => "Codasip"
"query_by" => "text_high_priority, text_low_priority"
"query_by_weights" => "100, 1"
"max_candidates" => 10000
"per_page" => 10
"page" => 1
"facet_by" => "provider.object, asic.foundry, asic.foundry_node, asic.node_foundry, asic.node, productTypes"
"max_facet_values" => 1000
"sort_by" => "_text_match:desc"
"prioritize_exact_match" => false
"text_match_type" => "max_weight"
]
1 => array:11 [
"q" => "Codasip"
"query_by" => "text_high_priority, text_low_priority"
"query_by_weights" => "100, 1"
"max_candidates" => 10000
"per_page" => 10
"page" => 1
"facet_by" => "provider.object, asic.foundry, asic.foundry_node, asic.node_foundry, asic.node, productTypes"
"max_facet_values" => 1000
"sort_by" => "_text_match:desc"
"prioritize_exact_match" => false
"text_match_type" => "max_weight"
]
2 => array:11 [
"q" => "Codasip"
"query_by" => "text_high_priority, text_low_priority"
"query_by_weights" => "100, 1"
"max_candidates" => 10000
"per_page" => 10
"page" => 1
"facet_by" => "provider.object, asic.foundry, asic.foundry_node, asic.node_foundry, asic.node, productTypes"
"max_facet_values" => 1000
"sort_by" => "_text_match:desc"
"prioritize_exact_match" => false
"text_match_type" => "max_weight"
]
]
]
array:1 [
"results" => array:3 [
0 => array:8 [
"facet_counts" => array:6 [
0 => array:4 [
"counts" => array:1 [
0 => array:3 [
"count" => 11
"highlighted" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"value" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
]
]
"field_name" => "provider.object"
"sampled" => false
"stats" => array:1 [
"total_values" => 1
]
]
1 => array:4 [
"counts" => []
"field_name" => "asic.foundry"
"sampled" => false
"stats" => array:1 [
"total_values" => 0
]
]
2 => array:4 [
"counts" => []
"field_name" => "asic.foundry_node"
"sampled" => false
"stats" => array:1 [
"total_values" => 0
]
]
3 => array:4 [
"counts" => []
"field_name" => "asic.node_foundry"
"sampled" => false
"stats" => array:1 [
"total_values" => 0
]
]
4 => array:4 [
"counts" => []
"field_name" => "asic.node"
"sampled" => false
"stats" => array:1 [
"total_values" => 0
]
]
5 => array:4 [
"counts" => array:1 [
0 => array:3 [
"count" => 11
"highlighted" => "sip"
"value" => "sip"
]
]
"field_name" => "productTypes"
"sampled" => false
"stats" => array:1 [
"total_values" => 1
]
]
]
"found" => 11
"hits" => array:10 [
0 => array:5 [
"document" => array:48 [
"asic.foundry" => []
"asic.foundry_node" => []
"asic.foundry_node_process" => []
"asic.node" => []
"asic.node_foundry" => []
"blockdiagram" => "/upload/catalog/product/blockdiagram/18819/icon_32-bit-embedded-risc-v-processor-core-66bb99ade2a8e.png.webp"
"category.id" => array:1 [
0 => 643
]
"category.name" => array:1 [
0 => "RISC-V Processor IP"
]
"category.slug" => []
"created_at" => 1723570603
"id" => "18819"
"keyfeatures" => """
<ul>\r\n
\t<li>Best-in-class performance for small-area and low-power applications\r\n
\t<ul>\r\n
\t\t<li>Delivering up to 50% improvements in performance per watt compared to similar cores in the market</li>\r\n
\t\t<li>Smaller and more performant than other RISC-V alternatives</li>\r\n
\t\t<li>Uses RISC-V standard extensions for area and code size reduction for additional power consumption reduction at system level</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Highly configurable and easy and quick to customize and verify\r\n
\t<ul>\r\n
\t\t<li>High-quality pre-verified baseline excellent for further configurations and</li>\r\n
\t\t<li>customization</li>\r\n
\t\t<li>Easy to customize and verify thanks to Codasip Studio Fusion</li>\r\n
\t\t<li>Customization is without risk, because the functionality of the baseline core is guaranteed</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Process compliant with ISO 26262 and ISO 21434\r\n
\t<ul>\r\n
\t\t<li>Developed using HW development process certified by TÜV SÜD</li>\r\n
\t\t<li>Development process certified for functional safety as well as cybersecurity</li>\r\n
\t</ul>\r\n
\t</li>\r\n
</ul>
"""
"keyfeatures_cn" => ""
"keywords" => "RISC-V processor, RISCV processor,RISC-V, RISCV"
"logo" => "codasip23-66bb478fde085.webp"
"logo2" => "codasip23-66bb478fde085.webp"
"name" => "asic.node"
"overview" => """
<p>Codasip® L110 is a 32-bit RISC-V embedded processor, focused on small-area and low-power applications.<br />\r\n
<br />\r\n
The core is highly configurable, allowing different area and performance levels, with optional support for standard RISC-V code size density extension.<br />\r\n
<br />\r\n
It is also fully customizable, and, when used in combination with Codasip Studio, it enables an easy and no-risk way to add custom instructions.</p>
"""
"overview_cn" => ""
"partnumber" => "Codasip L110"
"priority" => 61
"priority_taxo" => 1
"productTypes" => array:1 [
0 => "sip"
]
"provider.id" => 294
"provider.name" => "Codasip"
"provider.object" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"provider.priority" => 571
"provider.slug" => "codasip"
"published_as_new_at" => 0
"seofeatures" => """
<ul>\r\n
\t<li>Best-in-class performance for small-area and low-power applications</li>\r\n
\t<li>Highly configurable and easy and quick to customize and verify</li>\r\n
\t<li>Process compliant with ISO 26262 and ISO 21434</li>\r\n
</ul>
"""
"seofeatures_cn" => ""
"shortdescription" => "32 Bit - Embedded RISC-V Processor Core"
"shortdescription_cn" => ""
"slug" => "32-bit-embedded-risc-v-processor-core-1"
"sortable_id" => 18819
"taxo0" => array:1 [
0 => 1
]
"taxo1" => array:1 [
0 => 9
]
"taxo2" => array:1 [
0 => 99
]
"taxo3" => array:1 [
0 => 643
]
"taxo4" => []
"taxo5" => []
"taxo6" => []
"taxo7" => []
"taxo8" => []
"text_high_priority" => "Codasip L110 32 Bit - Embedded RISC-V Processor Core"
"text_low_priority" => """
Codasip® L110 is a 32-bit RISC-V embedded processor focused on small-area and low-power applications.\r\n
\r\n
The core highly configurable allowing different area performance levels with optional support for standard code size density extension.\r\n
\r\n
It also fully customizable when used in combination Codasip Studio it enables an easy no-risk way to add custom instructions. \r\n
\tBest-in-class applications\r\n
\t\r\n
\t\tDelivering up 50% improvements per watt compared similar cores the market\r\n
\t\tSmaller more performant than other alternatives\r\n
\t\tUses extensions reduction additional power consumption at system level\r\n
\t\r\n
\t\r\n
\tHighly quick customize verify\r\n
\t\r\n
\t\tHigh-quality pre-verified baseline excellent further configurations and\r\n
\t\tcustomization\r\n
\t\tEasy verify thanks Fusion\r\n
\t\tCustomization without risk because functionality of guaranteed\r\n
\t\r\n
\t\r\n
\tProcess compliant ISO 26262 21434\r\n
\t\r\n
\t\tDeveloped using HW development process certified by TÜV SÜD\r\n
\t\tDevelopment functional safety as well cybersecurity\r\n
\t\r\n
\t\r\n
"""
"text_medium_priority" => "RISC-V processor RISCV"
"updated_at" => 1724329863
]
"highlight" => array:2 [
"text_high_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> L110 32 Bit - Embedded RISC-V Processor Core"
]
"text_low_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark>® L110 is a 32-bit"
]
]
"highlights" => array:2 [
0 => array:3 [
"field" => "text_low_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark>® L110 is a 32-bit"
]
1 => array:3 [
"field" => "text_high_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> L110 32 Bit - Embedded RISC-V Processor Core"
]
]
"text_match" => 610246614239412226
"text_match_info" => array:7 [
"best_field_score" => "1108091338752"
"best_field_weight" => 15
"fields_matched" => 2
"num_tokens_dropped" => 0
"score" => "610246614239412226"
"tokens_matched" => 1
"typo_prefix_score" => 0
]
]
1 => array:5 [
"document" => array:48 [
"asic.foundry" => []
"asic.foundry_node" => []
"asic.foundry_node_process" => []
"asic.node" => []
"asic.node_foundry" => []
"blockdiagram" => "/upload/catalog/product/blockdiagram/15584/icon_32-bit-embedded-risc-v-processor-core-66bb8019afc14.png.webp"
"category.id" => array:1 [
0 => 643
]
"category.name" => array:1 [
0 => "RISC-V Processor IP"
]
"category.slug" => []
"created_at" => 1645714442
"id" => "15584"
"keyfeatures" => """
<ul>\r\n
\t<li>32-bit RISC-V core</li>\r\n
\t<li>Available in two versions:\r\n
\t<ul>\r\n
\t\t<li>RV32IMC</li>\r\n
\t\t<li>RV32IMCF</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>32 general purpose registers</li>\r\n
\t<li>Either parallel multiplier</li>\r\n
\t<li>3-stage pipeline</li>\r\n
\t<li>Dynamic branch predictor</li>\r\n
\t<li>RISC-V privilege mode support:\r\n
\t<ul>\r\n
\t\t<li>Machine, User</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Internal interrupt controller\r\n
\t<ul>\r\n
\t\t<li>Up to 256 sources</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Optional FPU (L30F)</li>\r\n
\t<li>Optional instruction and data tightly coupled memories (TCM)</li>\r\n
\t<li>Optional 8 or 16 PMP regions</li>\r\n
\t<li>Optional L1 data and instruction caches</li>\r\n
\t<li>Standard RISC-V CLINT\r\n
\t<ul>\r\n
\t\t<li>Up to 256 sources</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Wakeup interrupt controller</li>\r\n
\t<li>NMI</li>\r\n
\t<li>On-chip debugger\r\n
\t<ul>\r\n
\t\t<li>RISC-V Debug module</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>2/4 pin JTAG</li>\r\n
\t<li>2-8 breakpoints/watchpoints</li>\r\n
</ul>
"""
"keyfeatures_cn" => ""
"keywords" => "Processor, RISC-V, RISCV, Microcontroller"
"logo" => "codasip23-66bb478fde085.webp"
"logo2" => "codasip23-66bb478fde085.webp"
"name" => "asic.node"
"overview" => """
<p>The L31(F) is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requirements. The core has a 3-stage pipeline and has 32 general-purpose registers.<br />\r\n
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.<br />\r\n
Like with all Codasip RISC-V cores, it is possible to create custom instructions using Codasip Studio to extend the L31 and to generate corresponding hardware and software development kits.<br />\r\n
<br />\r\n
</p>
"""
"overview_cn" => ""
"partnumber" => "Codasip L31(F)"
"priority" => 91
"priority_taxo" => 1
"productTypes" => array:1 [
0 => "sip"
]
"provider.id" => 294
"provider.name" => "Codasip"
"provider.object" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"provider.priority" => 571
"provider.slug" => "codasip"
"published_as_new_at" => 0
"seofeatures" => """
<ul>\r\n
\t<li>32 bit,</li>\r\n
\t<li>3-stage pipeline,</li>\r\n
\t<li>32 registers</li>\r\n
</ul>
"""
"seofeatures_cn" => ""
"shortdescription" => "32 Bit - Embedded RISC-V Processor Core"
"shortdescription_cn" => ""
"slug" => "32-bit-embedded-risc-v-processor-core"
"sortable_id" => 15584
"taxo0" => array:1 [
0 => 1
]
"taxo1" => array:1 [
0 => 9
]
"taxo2" => array:1 [
0 => 99
]
"taxo3" => array:1 [
0 => 643
]
"taxo4" => []
"taxo5" => []
"taxo6" => []
"taxo7" => []
"taxo8" => []
"text_high_priority" => "Codasip L31(F) 32 Bit - Embedded RISC-V Processor Core"
"text_low_priority" => """
The L31(F) is a small efficient 32-bit embedded RISC-V processor aimed at systems with more modest processing requirements. core has 3-stage pipeline and 32 general-purpose registers.\r\n
The includes optional L1 data instruction caches TCM 8 or 16 PMP regions an interrupt controller Debug module optionally PC trace.\r\n
Like all Codasip cores it possible to create custom instructions using Studio extend the L31 generate corresponding hardware software development kits.\r\n
\r\n
\r\n
\t32-bit core\r\n
\tAvailable in two versions:\r\n
\t\r\n
\t\tRV32IMC\r\n
\t\tRV32IMCF\r\n
\t\r\n
\t\r\n
\t32 general purpose registers\r\n
\tEither parallel multiplier\r\n
\t3-stage pipeline\r\n
\tDynamic branch predictor\r\n
\tRISC-V privilege mode support:\r\n
\t\r\n
\t\tMachine User\r\n
\t\r\n
\t\r\n
\tInternal controller\r\n
\t\r\n
\t\tUp 256 sources\r\n
\t\r\n
\t\r\n
\tOptional FPU (L30F)\r\n
\tOptional tightly coupled memories (TCM)\r\n
\tOptional regions\r\n
\tOptional caches\r\n
\tStandard CLINT\r\n
\t\r\n
\t\tUp sources\r\n
\t\r\n
\t\r\n
\tWakeup controller\r\n
\tNMI\r\n
\tOn-chip debugger\r\n
\t\r\n
\t\tRISC-V module\r\n
\t\r\n
\t\r\n
\t2/4 pin JTAG\r\n
\t2-8 breakpoints/watchpoints\r\n
"""
"text_medium_priority" => "Processor RISC-V RISCV Microcontroller"
"updated_at" => 1724273456
]
"highlight" => array:2 [
"text_high_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> L31(F) 32 Bit - Embedded RISC-V Processor Core"
]
"text_low_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\r\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"highlights" => array:2 [
0 => array:3 [
"field" => "text_high_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> L31(F) 32 Bit - Embedded RISC-V Processor Core"
]
1 => array:3 [
"field" => "text_low_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\r\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"text_match" => 610246614239412226
"text_match_info" => array:7 [
"best_field_score" => "1108091338752"
"best_field_weight" => 15
"fields_matched" => 2
"num_tokens_dropped" => 0
"score" => "610246614239412226"
"tokens_matched" => 1
"typo_prefix_score" => 0
]
]
2 => array:5 [
"document" => array:48 [
"asic.foundry" => []
"asic.foundry_node" => []
"asic.foundry_node_process" => []
"asic.node" => []
"asic.node_foundry" => []
"blockdiagram" => "/upload/catalog/product/blockdiagram/15583/icon_32-bit-compact-risc-v-processor-core-66bb80167f6eb.png.webp"
"category.id" => array:1 [
0 => 643
]
"category.name" => array:1 [
0 => "RISC-V Processor IP"
]
"category.slug" => []
"created_at" => 1645714199
"id" => "15583"
"keyfeatures" => """
<ul>\r\n
\t<li>32-bit RISC-V core</li>\r\n
\t<li>RV32EMC instruction set</li>\r\n
\t<li>16 general purpose registers</li>\r\n
\t<li>Either small sequential multiplier</li>\r\n
\t<li>3-stage pipeline</li>\r\n
\t<li>RISC-V privilege mode support:\r\n
\t<ul>\r\n
\t\t<li>Machine</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Standard RISC-V CLINT\r\n
\t<ul>\r\n
\t\t<li>Up to 256 sources</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Wakeup interrupt controller</li>\r\n
\t<li>NMI</li>\r\n
\t<li>On-chip debugger\r\n
\t<ul>\r\n
\t\t<li>RISC-V Debug module</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>2/4 pin JTAG</li>\r\n
\t<li>2-8 breakpoints/watchpoints</li>\r\n
</ul>
"""
"keyfeatures_cn" => ""
"keywords" => "Processor, RISC-V, RISCV, Microcontroller"
"logo" => "codasip23-66bb478fde085.webp"
"logo2" => "codasip23-66bb478fde085.webp"
"name" => "asic.node"
"overview" => """
<p>The L11 is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requirements. The core has a 3-stage pipeline and with 16 general purpose registers.<br />\r\n
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.<br />\r\n
Like with all Codasip RISC-V cores, it is possible to create custom instructions using Codasip Studio to extend the L10 and to generate corresponding hardware and software development kits.<br />\r\n
</p>
"""
"overview_cn" => ""
"partnumber" => "Codasip L11"
"priority" => 91
"priority_taxo" => 1
"productTypes" => array:1 [
0 => "sip"
]
"provider.id" => 294
"provider.name" => "Codasip"
"provider.object" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"provider.priority" => 571
"provider.slug" => "codasip"
"published_as_new_at" => 0
"seofeatures" => """
<ul>\r\n
\t<li>32-bit RISC-V core</li>\r\n
\t<li>RV32EMC instruction set</li>\r\n
\t<li>16 general purpose registers</li>\r\n
</ul>
"""
"seofeatures_cn" => ""
"shortdescription" => "32 bit - Compact RISC-V Processor Core"
"shortdescription_cn" => ""
"slug" => "32-bit-compact-risc-v-processor-core"
"sortable_id" => 15583
"taxo0" => array:1 [
0 => 1
]
"taxo1" => array:1 [
0 => 9
]
"taxo2" => array:1 [
0 => 99
]
"taxo3" => array:1 [
0 => 643
]
"taxo4" => []
"taxo5" => []
"taxo6" => []
"taxo7" => []
"taxo8" => []
"text_high_priority" => "Codasip L11 32 bit - Compact RISC-V Processor Core"
"text_low_priority" => """
The L11 is a small efficient 32-bit embedded RISC-V processor aimed at systems with more modest processing requirements. core has 3-stage pipeline and 16 general purpose registers.\r\n
The includes optional L1 data instruction caches TCM 8 or PMP regions an interrupt controller Debug module optionally PC trace.\r\n
Like all Codasip cores it possible to create custom instructions using Studio extend the L10 generate corresponding hardware software development kits.\r\n
\r\n
\t32-bit core\r\n
\tRV32EMC set\r\n
\t16 registers\r\n
\tEither sequential multiplier\r\n
\t3-stage pipeline\r\n
\tRISC-V privilege mode support:\r\n
\t\r\n
\t\tMachine\r\n
\t\r\n
\t\r\n
\tStandard CLINT\r\n
\t\r\n
\t\tUp 256 sources\r\n
\t\r\n
\t\r\n
\tWakeup controller\r\n
\tNMI\r\n
\tOn-chip debugger\r\n
\t\r\n
\t\tRISC-V module\r\n
\t\r\n
\t\r\n
\t2/4 pin JTAG\r\n
\t2-8 breakpoints/watchpoints\r\n
"""
"text_medium_priority" => "Processor RISC-V RISCV Microcontroller"
"updated_at" => 1724329853
]
"highlight" => array:2 [
"text_high_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> L11 32 bit - Compact RISC-V Processor Core"
]
"text_low_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\r\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"highlights" => array:2 [
0 => array:3 [
"field" => "text_high_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> L11 32 bit - Compact RISC-V Processor Core"
]
1 => array:3 [
"field" => "text_low_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\r\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"text_match" => 610246614239412226
"text_match_info" => array:7 [
"best_field_score" => "1108091338752"
"best_field_weight" => 15
"fields_matched" => 2
"num_tokens_dropped" => 0
"score" => "610246614239412226"
"tokens_matched" => 1
"typo_prefix_score" => 0
]
]
3 => array:5 [
"document" => array:48 [
"asic.foundry" => []
"asic.foundry_node" => []
"asic.foundry_node_process" => []
"asic.node" => []
"asic.node_foundry" => []
"blockdiagram" => "/upload/catalog/product/blockdiagram/14641/icon_compact-risc-v-processor-32-bit-3-stage-pipeline-32-registers-66bb791106370.png.webp"
"category.id" => array:1 [
0 => 643
]
"category.name" => array:1 [
0 => "RISC-V Processor IP"
]
"category.slug" => []
"created_at" => 1614788957
"id" => "14641"
"keyfeatures" => """
<ul>\r\n
\t<li>32-bit RISC-V core</li>\r\n
\t<li>Available in two versions:\r\n
\t<ul>\r\n
\t\t<li>RV32IMC</li>\r\n
\t\t<li>RV32IMCF</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>32 general purpose registers</li>\r\n
\t<li>Either parallel multiplier</li>\r\n
\t<li>3-stage pipeline</li>\r\n
\t<li>Dynamic branch predictor</li>\r\n
\t<li>RISC-V privilege mode support:\r\n
\t<ul>\r\n
\t\t<li>Machine, User</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Internal interrupt controller\r\n
\t<ul>\r\n
\t\t<li>Up to 256 sources</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Optional FPU (L30F)</li>\r\n
\t<li>Optional instruction and data tightly coupled memories (TCM)</li>\r\n
\t<li>Optional 8 or 16 PMP regions</li>\r\n
\t<li>Optional L1 data and instruction caches</li>\r\n
\t<li>Standard RISC-V CLINT\r\n
\t<ul>\r\n
\t\t<li>Up to 256 sources</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Wakeup interrupt controller</li>\r\n
\t<li>NMI</li>\r\n
\t<li>On-chip debugger\r\n
\t<ul>\r\n
\t\t<li>RISC-V Debug module</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>2/4 pin JTAG</li>\r\n
\t<li>2-8 breakpoints/watchpoints</li>\r\n
</ul>
"""
"keyfeatures_cn" => ""
"keywords" => "Processor, RISC-V, RISCV, Microcontroller"
"logo" => "codasip23-66bb478fde085.webp"
"logo2" => "codasip23-66bb478fde085.webp"
"name" => "asic.node"
"overview" => """
<p>The L30(F) is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requirements. The core has a 3-stage pipeline and has 32 general-purpose registers.<br />\r\n
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.<br />\r\n
Like with all Codasip RISC-V cores, it is possible to create custom instructions using Codasip Studio to extend the L30 and to generate corresponding hardware and software development kits.<br />\r\n
</p>
"""
"overview_cn" => ""
"partnumber" => "Codasip L30(F)"
"priority" => 1
"priority_taxo" => 1
"productTypes" => array:1 [
0 => "sip"
]
"provider.id" => 294
"provider.name" => "Codasip"
"provider.object" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"provider.priority" => 571
"provider.slug" => "codasip"
"published_as_new_at" => 0
"seofeatures" => """
<ul>\r\n
\t<li>32-bit RISC-V core</li>\r\n
\t<li>Available in two versions:</li>\r\n
\t<li>32 general purpose registers</li>\r\n
\t<li>Either parallel multiplier</li>\r\n
</ul>
"""
"seofeatures_cn" => ""
"shortdescription" => "Compact RISC-V Processor - 32 bit, 3-stage pipeline, 32 registers"
"shortdescription_cn" => ""
"slug" => "compact-risc-v-processor-32-bit-3-stage-pipeline-32-registers"
"sortable_id" => 14641
"taxo0" => array:1 [
0 => 1
]
"taxo1" => array:1 [
0 => 9
]
"taxo2" => array:1 [
0 => 99
]
"taxo3" => array:1 [
0 => 643
]
"taxo4" => []
"taxo5" => []
"taxo6" => []
"taxo7" => []
"taxo8" => []
"text_high_priority" => "Codasip L30(F) Compact RISC-V Processor - 32 bit 3-stage pipeline registers"
"text_low_priority" => """
The L30(F) is a small efficient 32-bit embedded RISC-V processor aimed at systems with more modest processing requirements. core has 3-stage pipeline and 32 general-purpose registers.\r\n
The includes optional L1 data instruction caches TCM 8 or 16 PMP regions an interrupt controller Debug module optionally PC trace.\r\n
Like all Codasip cores it possible to create custom instructions using Studio extend the L30 generate corresponding hardware software development kits.\r\n
\r\n
\t32-bit core\r\n
\tAvailable in two versions:\r\n
\t\r\n
\t\tRV32IMC\r\n
\t\tRV32IMCF\r\n
\t\r\n
\t\r\n
\t32 general purpose registers\r\n
\tEither parallel multiplier\r\n
\t3-stage pipeline\r\n
\tDynamic branch predictor\r\n
\tRISC-V privilege mode support:\r\n
\t\r\n
\t\tMachine User\r\n
\t\r\n
\t\r\n
\tInternal controller\r\n
\t\r\n
\t\tUp 256 sources\r\n
\t\r\n
\t\r\n
\tOptional FPU (L30F)\r\n
\tOptional tightly coupled memories (TCM)\r\n
\tOptional regions\r\n
\tOptional caches\r\n
\tStandard CLINT\r\n
\t\r\n
\t\tUp sources\r\n
\t\r\n
\t\r\n
\tWakeup controller\r\n
\tNMI\r\n
\tOn-chip debugger\r\n
\t\r\n
\t\tRISC-V module\r\n
\t\r\n
\t\r\n
\t2/4 pin JTAG\r\n
\t2-8 breakpoints/watchpoints\r\n
"""
"text_medium_priority" => "Processor RISC-V RISCV Microcontroller"
"updated_at" => 1724274361
]
"highlight" => array:2 [
"text_high_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> L30(F) Compact RISC-V Processor - 32 bit 3-stage pipeline registers"
]
"text_low_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\r\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"highlights" => array:2 [
0 => array:3 [
"field" => "text_high_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> L30(F) Compact RISC-V Processor - 32 bit 3-stage pipeline registers"
]
1 => array:3 [
"field" => "text_low_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\r\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"text_match" => 610246614239412226
"text_match_info" => array:7 [
"best_field_score" => "1108091338752"
"best_field_weight" => 15
"fields_matched" => 2
"num_tokens_dropped" => 0
"score" => "610246614239412226"
"tokens_matched" => 1
"typo_prefix_score" => 0
]
]
4 => array:5 [
"document" => array:48 [
"asic.foundry" => []
"asic.foundry_node" => []
"asic.foundry_node_process" => []
"asic.node" => []
"asic.node_foundry" => []
"blockdiagram" => "/upload/catalog/product/blockdiagram/14236/icon_64-bit-risc-v-application-processor-core-66bb760b9ef28.png.webp"
"category.id" => array:1 [
0 => 643
]
"category.name" => array:1 [
0 => "RISC-V Processor IP"
]
"category.slug" => []
"created_at" => 1607105972
"id" => "14236"
"keyfeatures" => "<ul><li>64-bit RISC-V core</li><ul><li> RV64GC (GC=IMAFDC)</li></ul><li>Linux capable</li><li>In-order 7-stage pipeline</li><li>RISC-V mode support:</li><ul><li> Machine</li><li> Supervisor</li><li> User</li></ul><li>Internal interrupt controller</li><ul><li> Up to 256 sources</li></ul><li>Dynamic jump prediction</li><li>Optional FPU</li><li>Integrated L1 data and instruction caches</li><li>L2 cache coherence for up to 4 cores</li><li>MMU</li><li>On-chip debugger</li><ul><li> JTAG and RISC-V Debug module</li></ul><li>>1GHz clock in 22 nm</li></ul>"
"keyfeatures_cn" => ""
"keywords" => "RISC-V,RISCV,64-bit,Linux"
"logo" => "codasip23-66bb478fde085.webp"
"logo2" => "codasip23-66bb478fde085.webp"
"name" => "asic.node"
"overview" => """
The A70 is a powerful 64-bit RISC-V application processor aimed at systems running Linux. The core has an in-order 7-stage pipeline enabling greater than 1 GHz frequencies in 22nm HPC. <br />\n
The core includes integrated L1 data and instruction caches, an interrupt controller and RISC-V Debug module optionally with PC trace.<br />\n
Like all Codasip RISC-V cores it is possible to create custom instructions using Codasip Studio to extend the ISA and to generate corresponding hardware and software development kits.<br />\n
"""
"overview_cn" => ""
"partnumber" => "Codasip A70-MP"
"priority" => 41
"priority_taxo" => 1
"productTypes" => array:1 [
0 => "sip"
]
"provider.id" => 294
"provider.name" => "Codasip"
"provider.object" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"provider.priority" => 571
"provider.slug" => "codasip"
"published_as_new_at" => 0
"seofeatures" => "<ul><li>High computational throughput with 7-stage pipeline and branch predictor</li><li>Support for RISC-V single and double precision FPU</li></ul>"
"seofeatures_cn" => ""
"shortdescription" => "64-bit RISC-V Application Processor Core"
"shortdescription_cn" => ""
"slug" => "64-bit-risc-v-application-processor-core-1"
"sortable_id" => 14236
"taxo0" => array:1 [
0 => 1
]
"taxo1" => array:1 [
0 => 9
]
"taxo2" => array:1 [
0 => 99
]
"taxo3" => array:1 [
0 => 643
]
"taxo4" => []
"taxo5" => []
"taxo6" => []
"taxo7" => []
"taxo8" => []
"text_high_priority" => "Codasip A70-MP 64-bit RISC-V Application Processor Core"
"text_low_priority" => """
The A70 is a powerful 64-bit RISC-V application processor aimed at systems running Linux. core has an in-order 7-stage pipeline enabling greater than 1 GHz frequencies in 22nm HPC. \n
The includes integrated L1 data and instruction caches interrupt controller Debug module optionally with PC trace.\n
Like all Codasip cores it possible to create custom instructions using Studio extend the ISA generate corresponding hardware software development kits.\n
RV64GC (GC=IMAFDC)Linux capableIn-order pipelineRISC-V mode support: Machine Supervisor UserInternal Up 256 sourcesDynamic jump predictionOptional FPUIntegrated cachesL2 cache coherence for up 4 coresMMUOn-chip debugger JTAG module>1GHz clock 22 nm
"""
"text_medium_priority" => "RISC-V RISCV 64-bit Linux "
"updated_at" => 1695309751
]
"highlight" => array:2 [
"text_high_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> A70-MP 64-bit RISC-V Application Processor Core"
]
"text_low_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"highlights" => array:2 [
0 => array:3 [
"field" => "text_high_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> A70-MP 64-bit RISC-V Application Processor Core"
]
1 => array:3 [
"field" => "text_low_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"text_match" => 610246614239412226
"text_match_info" => array:7 [
"best_field_score" => "1108091338752"
"best_field_weight" => 15
"fields_matched" => 2
"num_tokens_dropped" => 0
"score" => "610246614239412226"
"tokens_matched" => 1
"typo_prefix_score" => 0
]
]
5 => array:5 [
"document" => array:48 [
"asic.foundry" => []
"asic.foundry_node" => []
"asic.foundry_node_process" => []
"asic.node" => []
"asic.node_foundry" => []
"blockdiagram" => "/upload/catalog/product/blockdiagram/14235/icon_64-bit-risc-v-application-processor-core-66bb76083e20a.png.webp"
"category.id" => array:1 [
0 => 643
]
"category.name" => array:1 [
0 => "RISC-V Processor IP"
]
"category.slug" => []
"created_at" => 1607105564
"id" => "14235"
"keyfeatures" => "<ul><li>64-bit RISC-V core</li><ul><li> RV64GC (GC=IMAFDC)</li></ul><li>Linux capable</li><li>In-order 7-stage pipeline</li><li>RISC-V mode support:</li><ul><li> Machine</li><li> Supervisor</li><li> User</li></ul><li>Internal interrupt controller</li><ul><li> Up to 256 sources</li></ul><li>Dynamic jump prediction</li><li>Optional FPU</li><li>Integrated L1 data and instruction caches</li><li>MMU</li><li>On-chip debugger</li><ul><li> JTAG and RISC-V Debug module</li></ul><li>>1GHz clock in 22 nm</li></ul>"
"keyfeatures_cn" => ""
"keywords" => "RISC-V,RISCV,64-bit,Linux"
"logo" => "codasip23-66bb478fde085.webp"
"logo2" => "codasip23-66bb478fde085.webp"
"name" => "asic.node"
"overview" => """
The A70 is a powerful 64-bit RISC-V application processor aimed at systems running Linux. The core has an in-order 7-stage pipeline enabling greater than 1 GHz frequencies in 22nm HPC. <br />\n
The core includes integrated L1 data and instruction caches, an interrupt controller and RISC-V Debug module optionally with PC trace.<br />\n
Like all Codasip RISC-V cores it is possible to create custom instructions using Codasip Studio to extend the ISA and to generate corresponding hardware and software development kits.<br />\n
Tensor Flow Lite Micro is supported<br />\n
"""
"overview_cn" => ""
"partnumber" => "Codasip A70"
"priority" => 101
"priority_taxo" => 1
"productTypes" => array:1 [
0 => "sip"
]
"provider.id" => 294
"provider.name" => "Codasip"
"provider.object" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"provider.priority" => 571
"provider.slug" => "codasip"
"published_as_new_at" => 0
"seofeatures" => "<ul><li>64-bit RISC-V core</li><li>Linux capable</li><li>In-order 7-stage pipeline</li></ul>"
"seofeatures_cn" => ""
"shortdescription" => "64-bit RISC-V Application Processor Core"
"shortdescription_cn" => ""
"slug" => "64-bit-risc-v-application-processor-core"
"sortable_id" => 14235
"taxo0" => array:1 [
0 => 1
]
"taxo1" => array:1 [
0 => 9
]
"taxo2" => array:1 [
0 => 99
]
"taxo3" => array:1 [
0 => 643
]
"taxo4" => []
"taxo5" => []
"taxo6" => []
"taxo7" => []
"taxo8" => []
"text_high_priority" => "Codasip A70 64-bit RISC-V Application Processor Core"
"text_low_priority" => """
The A70 is a powerful 64-bit RISC-V application processor aimed at systems running Linux. core has an in-order 7-stage pipeline enabling greater than 1 GHz frequencies in 22nm HPC. \n
The includes integrated L1 data and instruction caches interrupt controller Debug module optionally with PC trace.\n
Like all Codasip cores it possible to create custom instructions using Studio extend the ISA generate corresponding hardware software development kits.\n
Tensor Flow Lite Micro supported\n
RV64GC (GC=IMAFDC)Linux capableIn-order pipelineRISC-V mode support: Machine Supervisor UserInternal Up 256 sourcesDynamic jump predictionOptional FPUIntegrated cachesMMUOn-chip debugger JTAG module>1GHz clock 22 nm
"""
"text_medium_priority" => "RISC-V RISCV 64-bit Linux "
"updated_at" => 1695309729
]
"highlight" => array:2 [
"text_high_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> A70 64-bit RISC-V Application Processor Core"
]
"text_low_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"highlights" => array:2 [
0 => array:3 [
"field" => "text_high_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> A70 64-bit RISC-V Application Processor Core"
]
1 => array:3 [
"field" => "text_low_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"text_match" => 610246614239412226
"text_match_info" => array:7 [
"best_field_score" => "1108091338752"
"best_field_weight" => 15
"fields_matched" => 2
"num_tokens_dropped" => 0
"score" => "610246614239412226"
"tokens_matched" => 1
"typo_prefix_score" => 0
]
]
6 => array:5 [
"document" => array:48 [
"asic.foundry" => []
"asic.foundry_node" => []
"asic.foundry_node_process" => []
"asic.node" => []
"asic.node_foundry" => []
"blockdiagram" => "/upload/catalog/product/blockdiagram/13700/icon_processor-development-toolset-66bb724ab758f.png.webp"
"category.id" => array:1 [
0 => 643
]
"category.name" => array:1 [
0 => "RISC-V Processor IP"
]
"category.slug" => []
"created_at" => 1585330653
"id" => "13700"
"keyfeatures" => """
<ul>\r\n
\t<li>A unified development model describing the processor in a single CodAL description</li>\r\n
\t<li>High performance processor synthesis</li>\r\n
\t<li>Complete UVM verification environment</li>\r\n
\t<li>Advanced profiling and analysis</li>\r\n
\t<li>Compatible with Codasip RISC-V cores</li>\r\n
</ul>
"""
"keyfeatures_cn" => ""
"keywords" => "Processor, toolset, EDA, RISC-V, RISCV, ISS, SDK, HDK, UVM, CodAL, co-simulation,ASIP,domain-specific design"
"logo" => "codasip23-66bb478fde085.webp"
"logo2" => "codasip23-66bb478fde085.webp"
"name" => "asic.node"
"overview" => """
<p>Codasip Studio is a complete set of Electronic Design Automation (EDA) tools for processor design and customization. The level of automation is unmatched on the market, and produces fast and efficient results.<br />\r\n
<br />\r\n
Our approach at Codasip is to automate the development of processor cores by using a high-level description in the CodAL processor description language and generating the design implementation, verification environment, virtual system prototype, and a complete software toolchain using Codasip Studio.<br />\r\n
<br />\r\n
In addition to its design capabilities, Codasip Studio includes powerful multiprocessor programming, debugging and profiling features, enabling the development of complex processor designs with ease.<br />\r\n
<br />\r\n
Codasip Studio is built upon open standards and software including Eclipse, LLVM, Verilog, SystemVerilog, and UVM.</p>
"""
"overview_cn" => ""
"partnumber" => "Codasip Studio"
"priority" => 91
"priority_taxo" => 1
"productTypes" => array:1 [
0 => "sip"
]
"provider.id" => 294
"provider.name" => "Codasip"
"provider.object" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"provider.priority" => 571
"provider.slug" => "codasip"
"published_as_new_at" => 0
"seofeatures" => """
<ul>\r\n
\t<li>A unified development model describing the processor in a single CodAL description</li>\r\n
\t<li>High performance processor synthesis</li>\r\n
\t<li>Complete UVM verification environment</li>\r\n
\t<li>Advanced profiling and analysis</li>\r\n
</ul>
"""
"seofeatures_cn" => ""
"shortdescription" => "Processor Development Toolset"
"shortdescription_cn" => ""
"slug" => "processor-development-toolset"
"sortable_id" => 13700
"taxo0" => array:1 [
0 => 1
]
"taxo1" => array:1 [
0 => 9
]
"taxo2" => array:1 [
0 => 99
]
"taxo3" => array:1 [
0 => 643
]
"taxo4" => []
"taxo5" => []
"taxo6" => []
"taxo7" => []
"taxo8" => []
"text_high_priority" => "Codasip Studio Processor Development Toolset"
"text_low_priority" => """
Codasip Studio is a complete set of Electronic Design Automation (EDA) tools for processor design and customization. The level automation unmatched on the market produces fast efficient results.\r\n
\r\n
Our approach at to automate development cores by using high-level description in CodAL language generating implementation verification environment virtual system prototype software toolchain Studio.\r\n
\r\n
In addition its capabilities includes powerful multiprocessor programming debugging profiling features enabling complex designs with ease.\r\n
\r\n
Codasip built upon open standards including Eclipse LLVM Verilog SystemVerilog UVM. \r\n
\tA unified model describing single description\r\n
\tHigh performance synthesis\r\n
\tComplete UVM environment\r\n
\tAdvanced analysis\r\n
\tCompatible RISC-V cores\r\n
"""
"text_medium_priority" => "Processor toolset EDA RISC-V RISCV ISS SDK HDK UVM CodAL co-simulation ASIP domain-specific design"
"updated_at" => 1724273514
]
"highlight" => array:2 [
"text_high_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> Studio Processor Development Toolset"
]
"text_low_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> Studio is a complete"
]
]
"highlights" => array:2 [
0 => array:3 [
"field" => "text_high_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> Studio Processor Development Toolset"
]
1 => array:3 [
"field" => "text_low_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> Studio is a complete"
]
]
"text_match" => 610246614239412226
"text_match_info" => array:7 [
"best_field_score" => "1108091338752"
"best_field_weight" => 15
"fields_matched" => 2
"num_tokens_dropped" => 0
"score" => "610246614239412226"
"tokens_matched" => 1
"typo_prefix_score" => 0
]
]
7 => array:5 [
"document" => array:48 [
"asic.foundry" => []
"asic.foundry_node" => []
"asic.foundry_node_process" => []
"asic.node" => []
"asic.node_foundry" => []
"blockdiagram" => "/upload/catalog/product/blockdiagram/11810/icon_compact-efficient-64-bit-risc-v-processor-with-5-stage-pipeline-66bb6723b03a8.png.webp"
"category.id" => array:1 [
0 => 643
]
"category.name" => array:1 [
0 => "RISC-V Processor IP"
]
"category.slug" => []
"created_at" => 1511859747
"id" => "11810"
"keyfeatures" => "<ul><li>64-bit RISC-V core</li><ul><li> H50X supports RV64IMC</li><li> H50XF supports RV64IMCF</li></ul><li>Fully parallel multiplier</li><li>5-stage pipeline</li><li>Dynamic Branch Predictor</li><li>RISC-V mode support:</li><ul><li> Machine, User</li></ul><li>Internal interrupt controller</li><ul><li> Up to 256 sources</li></ul><li>FPU (H50F)</li><li>Optional instruction and data tightly coupled memories (TCM)</li><li>Optional 8 or 16 PMP regions</li><li>Optional L1 data and instruction caches</li><li>On-chip debugger</li><ul><li> JTAG and RISC-V Debug module</li></ul></ul>"
"keyfeatures_cn" => ""
"keywords" => "RISC-V, RISCV, Processor"
"logo" => "codasip23-66bb478fde085.webp"
"logo2" => "codasip23-66bb478fde085.webp"
"name" => "asic.node"
"overview" => """
The H50 is an entry level, compact, efficient 64-bit embedded RISC-V processor aimed at embedded systems requiring a large address space. The core has a 5-stage pipeline and is offered in two versions. <br />\n
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.<br />\n
Like with all Codasip RISC-V cores, it is possible to create custom instructions using Codasip Studio to extend the H50 and to generate corresponding hardware and software development kits.<br />\n
"""
"overview_cn" => ""
"partnumber" => "Codasip H50(F)"
"priority" => 1
"priority_taxo" => 1
"productTypes" => array:1 [
0 => "sip"
]
"provider.id" => 294
"provider.name" => "Codasip"
"provider.object" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"provider.priority" => 571
"provider.slug" => "codasip"
"published_as_new_at" => 0
"seofeatures" => "<ul><li>Support for RV32IM</li><li>5-stage pipeline</li><li>Thirty-two 64-bit general purpose registers</li></ul>"
"seofeatures_cn" => ""
"shortdescription" => "Compact, efficient 64-bit RISC-V processor with 5-stage pipeline"
"shortdescription_cn" => ""
"slug" => "compact-efficient-64-bit-risc-v-processor-with-5-stage-pipeline"
"sortable_id" => 11810
"taxo0" => array:1 [
0 => 1
]
"taxo1" => array:1 [
0 => 9
]
"taxo2" => array:1 [
0 => 99
]
"taxo3" => array:1 [
0 => 643
]
"taxo4" => []
"taxo5" => []
"taxo6" => []
"taxo7" => []
"taxo8" => []
"text_high_priority" => "Codasip H50(F) Compact efficient 64-bit RISC-V processor with 5-stage pipeline"
"text_low_priority" => """
The H50 is an entry level compact efficient 64-bit embedded RISC-V processor aimed at systems requiring a large address space. core has 5-stage pipeline and offered in two versions. \n
The includes optional L1 data instruction caches TCM 8 or 16 PMP regions interrupt controller Debug module optionally with PC trace.\n
Like all Codasip cores it possible to create custom instructions using Studio extend the generate corresponding hardware software development kits.\n
H50X supports RV64IMC H50XF RV64IMCFFully parallel multiplier5-stage pipelineDynamic Branch PredictorRISC-V mode support: Machine UserInternal Up 256 sourcesFPU (H50F)Optional tightly coupled memories (TCM)Optional regionsOptional cachesOn-chip debugger JTAG
"""
"text_medium_priority" => "RISC-V RISCV Processor"
"updated_at" => 1694450608
]
"highlight" => array:2 [
"text_high_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> H50(F) Compact efficient 64-bit RISC-V processor with 5-stage pipeline"
]
"text_low_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"highlights" => array:2 [
0 => array:3 [
"field" => "text_high_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> H50(F) Compact efficient 64-bit RISC-V processor with 5-stage pipeline"
]
1 => array:3 [
"field" => "text_low_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"text_match" => 610246614239412226
"text_match_info" => array:7 [
"best_field_score" => "1108091338752"
"best_field_weight" => 15
"fields_matched" => 2
"num_tokens_dropped" => 0
"score" => "610246614239412226"
"tokens_matched" => 1
"typo_prefix_score" => 0
]
]
8 => array:5 [
"document" => array:48 [
"asic.foundry" => []
"asic.foundry_node" => []
"asic.foundry_node_process" => []
"asic.node" => []
"asic.node_foundry" => []
"blockdiagram" => "/upload/catalog/product/blockdiagram/9729/icon_risc-v-processor-32-bit-5-stage-pipeline-66bb5e01b1d4d.png.webp"
"category.id" => array:1 [
0 => 643
]
"category.name" => array:1 [
0 => "RISC-V Processor IP"
]
"category.slug" => []
"created_at" => 1477431465
"id" => "9729"
"keyfeatures" => """
<ul>\r\n
\t<li>32-bit RISC-V core\r\n
\t<ul>\r\n
\t\t<li>The L50 supports the RV32IMC ISA</li>\r\n
\t\t<li>The L50F supports the RV32IMCF ISA</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Fully parallel multiplier</li>\r\n
\t<li>5-stage pipeline</li>\r\n
\t<li>Dynamic Branch Predictor</li>\r\n
\t<li>RISC-V privilege mode support:\r\n
\t<ul>\r\n
\t\t<li>Machine, User</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Internal interrupt controller\r\n
\t<ul>\r\n
\t\t<li>Up to 256 sources</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Optional FPU (L50F)</li>\r\n
\t<li>Optional instruction and data tightly coupled memories (TCM)</li>\r\n
\t<li>Optional 8 or 16 PMP regions</li>\r\n
\t<li>Optional L1 data and instruction caches</li>\r\n
\t<li>On-chip debugger\r\n
\t<ul>\r\n
\t\t<li>JTAG and RISC-V Debug module</li>\r\n
\t</ul>\r\n
\t</li>\r\n
</ul>
"""
"keyfeatures_cn" => ""
"keywords" => "RISC-V, RISCV, Processor"
"logo" => "codasip23-66bb478fde085.webp"
"logo2" => "codasip23-66bb478fde085.webp"
"name" => "asic.node"
"overview" => """
<p>The L50(F) is a medium-sized, efficient 32-bit embedded RISC-V processor aimed at embedded systems with mid-range processing requirements. The core has a 5-stage pipeline. The L50F has a floating point unit.<br />\r\n
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.<br />\r\n
Like with all Codasip RISC-V cores, it is possible to create custom instructions using Codasip Studio to extend the L50 or L50F and to generate corresponding hardware and software development kits.</p>
"""
"overview_cn" => ""
"partnumber" => "Codasip L50(F)"
"priority" => 1
"priority_taxo" => 1
"productTypes" => array:1 [
0 => "sip"
]
"provider.id" => 294
"provider.name" => "Codasip"
"provider.object" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"provider.priority" => 571
"provider.slug" => "codasip"
"published_as_new_at" => 0
"seofeatures" => """
<ul>\r\n
\t<li>Support for RV32IM/RV64IM</li>\r\n
\t<li>5-stage pipeline</li>\r\n
\t<li>32 or 64bit general purpose registers</li>\r\n
</ul>
"""
"seofeatures_cn" => ""
"shortdescription" => "RISC-V processor - 32 bit, 5-stage pipeline"
"shortdescription_cn" => ""
"slug" => "risc-v-processor-32-bit-5-stage-pipeline"
"sortable_id" => 9729
"taxo0" => array:1 [
0 => 1
]
"taxo1" => array:1 [
0 => 9
]
"taxo2" => array:1 [
0 => 99
]
"taxo3" => array:1 [
0 => 643
]
"taxo4" => []
"taxo5" => []
"taxo6" => []
"taxo7" => []
"taxo8" => []
"text_high_priority" => "Codasip L50(F) RISC-V processor - 32 bit 5-stage pipeline"
"text_low_priority" => """
The L50(F) is a medium-sized efficient 32-bit embedded RISC-V processor aimed at systems with mid-range processing requirements. core has 5-stage pipeline. L50F floating point unit.\r\n
The includes optional L1 data and instruction caches TCM 8 or 16 PMP regions an interrupt controller Debug module optionally PC trace.\r\n
Like all Codasip cores it possible to create custom instructions using Studio extend the L50 generate corresponding hardware software development kits. \r\n
\t32-bit core\r\n
\t\r\n
\t\tThe supports RV32IMC ISA\r\n
\t\tThe RV32IMCF ISA\r\n
\t\r\n
\t\r\n
\tFully parallel multiplier\r\n
\t5-stage pipeline\r\n
\tDynamic Branch Predictor\r\n
\tRISC-V privilege mode support:\r\n
\t\r\n
\t\tMachine User\r\n
\t\r\n
\t\r\n
\tInternal controller\r\n
\t\r\n
\t\tUp 256 sources\r\n
\t\r\n
\t\r\n
\tOptional FPU (L50F)\r\n
\tOptional tightly coupled memories (TCM)\r\n
\tOptional regions\r\n
\tOptional caches\r\n
\tOn-chip debugger\r\n
\t\r\n
\t\tJTAG module\r\n
\t\r\n
\t\r\n
"""
"text_medium_priority" => "RISC-V RISCV Processor"
"updated_at" => 1724273763
]
"highlight" => array:2 [
"text_high_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> L50(F) RISC-V processor - 32 bit 5-stage pipeline"
]
"text_low_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\r\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"highlights" => array:2 [
0 => array:3 [
"field" => "text_high_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> L50(F) RISC-V processor - 32 bit 5-stage pipeline"
]
1 => array:3 [
"field" => "text_low_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\r\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"text_match" => 610246614239412226
"text_match_info" => array:7 [
"best_field_score" => "1108091338752"
"best_field_weight" => 15
"fields_matched" => 2
"num_tokens_dropped" => 0
"score" => "610246614239412226"
"tokens_matched" => 1
"typo_prefix_score" => 0
]
]
9 => array:5 [
"document" => array:48 [
"asic.foundry" => []
"asic.foundry_node" => []
"asic.foundry_node_process" => []
"asic.node" => []
"asic.node_foundry" => []
"blockdiagram" => "/upload/catalog/product/blockdiagram/18735/icon_picture2-3-674b14421d6b0.png.webp"
"category.id" => array:1 [
0 => 643
]
"category.name" => array:1 [
0 => "RISC-V Processor IP"
]
"category.slug" => []
"created_at" => 1714399022
"id" => "18735"
"keyfeatures" => """
<ul>\r\n
\t<li>Flexible use cases\r\n
\t<ul>\r\n
\t\t<li>Safety Island as a protected enclave of the device providing freedom of interface for the independent execution of safety-related application code. </li>\r\n
\t\t<li>Controller, running the safety-related application code. </li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Proven technology\r\n
\t<ul>\r\n
\t\t<li>Based on the L31 silicon-proven embedded processor </li>\r\n
\t\t<li>State-of-the-art verification scheme brings quality and reliability </li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>State-of-the-art safety and security\r\n
\t<ul>\r\n
\t\t<li>Dual-core lockstep provides a robust and well trusted approach to building high-reliability systems and meeting the stringent safety requirements of critical applications </li>\r\n
\t\t<li>\u{200B}L31AS increases security against certain threat scenarios and can help meet requirements for security certification </li>\r\n
\t</ul>\r\n
\t</li>\r\n
</ul>
"""
"keyfeatures_cn" => ""
"keywords" => "Processor, RISC-V, RISCV, Microcontroller, TuV SuD ISO 26262"
"logo" => "codasip23-66bb478fde085.webp"
"logo2" => "codasip23-66bb478fde085.webp"
"name" => "asic.node"
"overview" => """
<p>The L31AS is a 32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification. Part of our safety and security offering, this embedded processor is ideal either as a Main Controller or a Safety Island in a Functional Safety System.<br />\r\n
<br />\r\n
It includes 2 instances of the L31 in a dual-core lockstep configuration along with Physical Memory Protection as a security feature.<br />\r\n
</p>\r\n
\r\n
<p>L31AS is an in-order, 3-stage, single-issue RISC-V core targeted for automotive and other functional safety applications. It is based on the RV32IMC ISA. It includes physical memory protection. </p>\r\n
\r\n
<p>L31AS features separate Data and Instruction AHB-Lite interfaces, block-level gating in single-core configuration and performance counters. It uses the standard RISC-V debug specification with 4 debug triggers and Debug Memory Interface (DMI) as an APB interface that can be used to interface with external debuggers. </p>\r\n
\r\n
<p><strong>Certified for Functional Safety</strong></p>\r\n
\r\n
<p>The L31AS core is certified by TÜV SÜD according to the requirements set forth in ISO26262 up to ASIL B. It is delivered with a safety pack including a safety manual and a safety case report. </p>\r\n
\r\n
<p><strong>Software development</strong></p>\r\n
\r\n
<p>Using standard AMBA AHB Interface, L31AS can easily be connected to existing systems and interconnects.\u{202F}What is more, L31AS is designed to simplify software development, with essential features to support developers:\u{202F} </p>\r\n
\r\n
<ul>\r\n
\t<li><strong>Debug interface</strong>\u{202F}– using standard RISC-V Debug specification\u{202F}\u{202F} </li>\r\n
\t<li><strong>Instruction-accurate model</strong>\u{202F}–\u{202F}for fast execution of software, before hardware is available\u{202F} </li>\r\n
\t<li><strong>Cycle-accurate model</strong>\u{202F}–\u{202F}for software algorithm optimization, when time constraints require precise execution\u{202F} </li>\r\n
\t<li><strong>Full trace capability</strong>\u{202F}– in the cycle-accurate model, to hunt hard-to-find bugs\u{202F} </li>\r\n
</ul>
"""
"overview_cn" => ""
"partnumber" => "Codasip L31AS"
"priority" => 1
"priority_taxo" => 1
"productTypes" => array:1 [
0 => "sip"
]
"provider.id" => 294
"provider.name" => "Codasip"
"provider.object" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"provider.priority" => 571
"provider.slug" => "codasip"
"published_as_new_at" => 0
"seofeatures" => """
<ul>\r\n
\t<li>Flexible use cases</li>\r\n
\t<li>roven technology</li>\r\n
\t<li>State-of-the-art safety and security\r\n
\t<ul>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<br />\r\n
\t<br />\r\n
\t<br />\r\n
\t \r\n
\t<li> </li>\r\n
</ul>
"""
"seofeatures_cn" => ""
"shortdescription" => "32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification"
"shortdescription_cn" => ""
"slug" => "32-bit-risc-v-embedded-processor-with-tuv-sud-iso-26262-asil-b-certification"
"sortable_id" => 18735
"taxo0" => array:1 [
0 => 1
]
"taxo1" => array:1 [
0 => 9
]
"taxo2" => array:1 [
0 => 99
]
"taxo3" => array:1 [
0 => 643
]
"taxo4" => []
"taxo5" => []
"taxo6" => []
"taxo7" => []
"taxo8" => []
"text_high_priority" => "Codasip L31AS 32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification"
"text_low_priority" => """
The L31AS is a 32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification. Part of our safety and security offering this ideal either as Main Controller or Safety Island in Functional System.\r\n
\r\n
It includes 2 instances the L31 dual-core lockstep configuration along Physical Memory Protection feature.\r\n
\r\n
\r\n
L31AS an in-order 3-stage single-issue core targeted for automotive other functional applications. It based on RV32IMC ISA. physical memory protection. \r\n
\r\n
L31AS features separate Data Instruction AHB-Lite interfaces block-level gating single-core performance counters. uses standard debug specification 4 triggers Debug Interface (DMI) APB interface that can be used to external debuggers. \r\n
\r\n
Certified Safety\r\n
\r\n
The certified by according requirements set forth in ISO26262 up B. delivered pack including manual case report. \r\n
\r\n
Software development\r\n
\r\n
Using AMBA AHB easily connected existing systems interconnects.\u{202F}What more designed simplify software development essential support developers:\u{202F} \r\n
\r\n
\r\n
\tDebug interface\u{202F}– using specification\u{202F}\u{202F} \r\n
\tInstruction-accurate model\u{202F}–\u{202F}for fast execution before hardware available\u{202F} \r\n
\tCycle-accurate algorithm optimization when time constraints require precise execution\u{202F} \r\n
\tFull trace capability\u{202F}– cycle-accurate model hunt hard-to-find bugs\u{202F} \r\n
\r\n
\tFlexible use cases\r\n
\t\r\n
\t\tSafety Island as protected enclave device providing freedom independent safety-related application code. \r\n
\t\tController running code. \r\n
\t\r\n
\t\r\n
\tProven technology\r\n
\t\r\n
\t\tBased silicon-proven embedded processor \r\n
\t\tState-of-the-art verification scheme brings quality reliability \r\n
\t\r\n
\t\r\n
\tState-of-the-art security\r\n
\t\r\n
\t\tDual-core provides robust well trusted approach building high-reliability meeting stringent requirements critical applications \r\n
\t\t\u{200B}L31AS increases against certain threat scenarios help meet certification \r\n
\t\r\n
\t\r\n
"""
"text_medium_priority" => "Processor RISC-V RISCV Microcontroller TuV SuD ISO 26262"
"updated_at" => 1732977234
]
"highlight" => array:1 [
"text_high_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> L31AS 32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification"
]
]
"highlights" => array:1 [
0 => array:3 [
"field" => "text_high_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> L31AS 32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification"
]
]
"text_match" => 610246614239412225
"text_match_info" => array:7 [
"best_field_score" => "1108091338752"
"best_field_weight" => 15
"fields_matched" => 1
"num_tokens_dropped" => 0
"score" => "610246614239412225"
"tokens_matched" => 1
"typo_prefix_score" => 0
]
]
]
"out_of" => 18250
"page" => 1
"request_params" => array:4 [
"collection_name" => "product_semiiphub"
"first_q" => "Codasip"
"per_page" => 10
"q" => "Codasip"
]
"search_cutoff" => false
"search_time_ms" => 3
]
1 => array:8 [
"facet_counts" => array:6 [
0 => array:4 [
"counts" => array:1 [
0 => array:3 [
"count" => 11
"highlighted" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"value" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
]
]
"field_name" => "provider.object"
"sampled" => false
"stats" => array:1 [
"total_values" => 1
]
]
1 => array:4 [
"counts" => []
"field_name" => "asic.foundry"
"sampled" => false
"stats" => array:1 [
"total_values" => 0
]
]
2 => array:4 [
"counts" => []
"field_name" => "asic.foundry_node"
"sampled" => false
"stats" => array:1 [
"total_values" => 0
]
]
3 => array:4 [
"counts" => []
"field_name" => "asic.node_foundry"
"sampled" => false
"stats" => array:1 [
"total_values" => 0
]
]
4 => array:4 [
"counts" => []
"field_name" => "asic.node"
"sampled" => false
"stats" => array:1 [
"total_values" => 0
]
]
5 => array:4 [
"counts" => array:1 [
0 => array:3 [
"count" => 11
"highlighted" => "sip"
"value" => "sip"
]
]
"field_name" => "productTypes"
"sampled" => false
"stats" => array:1 [
"total_values" => 1
]
]
]
"found" => 11
"hits" => array:10 [
0 => array:5 [
"document" => array:48 [
"asic.foundry" => []
"asic.foundry_node" => []
"asic.foundry_node_process" => []
"asic.node" => []
"asic.node_foundry" => []
"blockdiagram" => "/upload/catalog/product/blockdiagram/18819/icon_32-bit-embedded-risc-v-processor-core-66bb99ade2a8e.png.webp"
"category.id" => array:1 [
0 => 643
]
"category.name" => array:1 [
0 => "RISC-V Processor IP"
]
"category.slug" => []
"created_at" => 1723570603
"id" => "18819"
"keyfeatures" => """
<ul>\r\n
\t<li>Best-in-class performance for small-area and low-power applications\r\n
\t<ul>\r\n
\t\t<li>Delivering up to 50% improvements in performance per watt compared to similar cores in the market</li>\r\n
\t\t<li>Smaller and more performant than other RISC-V alternatives</li>\r\n
\t\t<li>Uses RISC-V standard extensions for area and code size reduction for additional power consumption reduction at system level</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Highly configurable and easy and quick to customize and verify\r\n
\t<ul>\r\n
\t\t<li>High-quality pre-verified baseline excellent for further configurations and</li>\r\n
\t\t<li>customization</li>\r\n
\t\t<li>Easy to customize and verify thanks to Codasip Studio Fusion</li>\r\n
\t\t<li>Customization is without risk, because the functionality of the baseline core is guaranteed</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Process compliant with ISO 26262 and ISO 21434\r\n
\t<ul>\r\n
\t\t<li>Developed using HW development process certified by TÜV SÜD</li>\r\n
\t\t<li>Development process certified for functional safety as well as cybersecurity</li>\r\n
\t</ul>\r\n
\t</li>\r\n
</ul>
"""
"keyfeatures_cn" => ""
"keywords" => "RISC-V processor, RISCV processor,RISC-V, RISCV"
"logo" => "codasip23-66bb478fde085.webp"
"logo2" => "codasip23-66bb478fde085.webp"
"name" => "asic.node"
"overview" => """
<p>Codasip® L110 is a 32-bit RISC-V embedded processor, focused on small-area and low-power applications.<br />\r\n
<br />\r\n
The core is highly configurable, allowing different area and performance levels, with optional support for standard RISC-V code size density extension.<br />\r\n
<br />\r\n
It is also fully customizable, and, when used in combination with Codasip Studio, it enables an easy and no-risk way to add custom instructions.</p>
"""
"overview_cn" => ""
"partnumber" => "Codasip L110"
"priority" => 61
"priority_taxo" => 1
"productTypes" => array:1 [
0 => "sip"
]
"provider.id" => 294
"provider.name" => "Codasip"
"provider.object" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"provider.priority" => 571
"provider.slug" => "codasip"
"published_as_new_at" => 0
"seofeatures" => """
<ul>\r\n
\t<li>Best-in-class performance for small-area and low-power applications</li>\r\n
\t<li>Highly configurable and easy and quick to customize and verify</li>\r\n
\t<li>Process compliant with ISO 26262 and ISO 21434</li>\r\n
</ul>
"""
"seofeatures_cn" => ""
"shortdescription" => "32 Bit - Embedded RISC-V Processor Core"
"shortdescription_cn" => ""
"slug" => "32-bit-embedded-risc-v-processor-core-1"
"sortable_id" => 18819
"taxo0" => array:1 [
0 => 1
]
"taxo1" => array:1 [
0 => 9
]
"taxo2" => array:1 [
0 => 99
]
"taxo3" => array:1 [
0 => 643
]
"taxo4" => []
"taxo5" => []
"taxo6" => []
"taxo7" => []
"taxo8" => []
"text_high_priority" => "Codasip L110 32 Bit - Embedded RISC-V Processor Core"
"text_low_priority" => """
Codasip® L110 is a 32-bit RISC-V embedded processor focused on small-area and low-power applications.\r\n
\r\n
The core highly configurable allowing different area performance levels with optional support for standard code size density extension.\r\n
\r\n
It also fully customizable when used in combination Codasip Studio it enables an easy no-risk way to add custom instructions. \r\n
\tBest-in-class applications\r\n
\t\r\n
\t\tDelivering up 50% improvements per watt compared similar cores the market\r\n
\t\tSmaller more performant than other alternatives\r\n
\t\tUses extensions reduction additional power consumption at system level\r\n
\t\r\n
\t\r\n
\tHighly quick customize verify\r\n
\t\r\n
\t\tHigh-quality pre-verified baseline excellent further configurations and\r\n
\t\tcustomization\r\n
\t\tEasy verify thanks Fusion\r\n
\t\tCustomization without risk because functionality of guaranteed\r\n
\t\r\n
\t\r\n
\tProcess compliant ISO 26262 21434\r\n
\t\r\n
\t\tDeveloped using HW development process certified by TÜV SÜD\r\n
\t\tDevelopment functional safety as well cybersecurity\r\n
\t\r\n
\t\r\n
"""
"text_medium_priority" => "RISC-V processor RISCV"
"updated_at" => 1724329863
]
"highlight" => array:2 [
"text_high_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> L110 32 Bit - Embedded RISC-V Processor Core"
]
"text_low_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark>® L110 is a 32-bit"
]
]
"highlights" => array:2 [
0 => array:3 [
"field" => "text_low_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark>® L110 is a 32-bit"
]
1 => array:3 [
"field" => "text_high_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> L110 32 Bit - Embedded RISC-V Processor Core"
]
]
"text_match" => 610246614239412226
"text_match_info" => array:7 [
"best_field_score" => "1108091338752"
"best_field_weight" => 15
"fields_matched" => 2
"num_tokens_dropped" => 0
"score" => "610246614239412226"
"tokens_matched" => 1
"typo_prefix_score" => 0
]
]
1 => array:5 [
"document" => array:48 [
"asic.foundry" => []
"asic.foundry_node" => []
"asic.foundry_node_process" => []
"asic.node" => []
"asic.node_foundry" => []
"blockdiagram" => "/upload/catalog/product/blockdiagram/15584/icon_32-bit-embedded-risc-v-processor-core-66bb8019afc14.png.webp"
"category.id" => array:1 [
0 => 643
]
"category.name" => array:1 [
0 => "RISC-V Processor IP"
]
"category.slug" => []
"created_at" => 1645714442
"id" => "15584"
"keyfeatures" => """
<ul>\r\n
\t<li>32-bit RISC-V core</li>\r\n
\t<li>Available in two versions:\r\n
\t<ul>\r\n
\t\t<li>RV32IMC</li>\r\n
\t\t<li>RV32IMCF</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>32 general purpose registers</li>\r\n
\t<li>Either parallel multiplier</li>\r\n
\t<li>3-stage pipeline</li>\r\n
\t<li>Dynamic branch predictor</li>\r\n
\t<li>RISC-V privilege mode support:\r\n
\t<ul>\r\n
\t\t<li>Machine, User</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Internal interrupt controller\r\n
\t<ul>\r\n
\t\t<li>Up to 256 sources</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Optional FPU (L30F)</li>\r\n
\t<li>Optional instruction and data tightly coupled memories (TCM)</li>\r\n
\t<li>Optional 8 or 16 PMP regions</li>\r\n
\t<li>Optional L1 data and instruction caches</li>\r\n
\t<li>Standard RISC-V CLINT\r\n
\t<ul>\r\n
\t\t<li>Up to 256 sources</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Wakeup interrupt controller</li>\r\n
\t<li>NMI</li>\r\n
\t<li>On-chip debugger\r\n
\t<ul>\r\n
\t\t<li>RISC-V Debug module</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>2/4 pin JTAG</li>\r\n
\t<li>2-8 breakpoints/watchpoints</li>\r\n
</ul>
"""
"keyfeatures_cn" => ""
"keywords" => "Processor, RISC-V, RISCV, Microcontroller"
"logo" => "codasip23-66bb478fde085.webp"
"logo2" => "codasip23-66bb478fde085.webp"
"name" => "asic.node"
"overview" => """
<p>The L31(F) is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requirements. The core has a 3-stage pipeline and has 32 general-purpose registers.<br />\r\n
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.<br />\r\n
Like with all Codasip RISC-V cores, it is possible to create custom instructions using Codasip Studio to extend the L31 and to generate corresponding hardware and software development kits.<br />\r\n
<br />\r\n
</p>
"""
"overview_cn" => ""
"partnumber" => "Codasip L31(F)"
"priority" => 91
"priority_taxo" => 1
"productTypes" => array:1 [
0 => "sip"
]
"provider.id" => 294
"provider.name" => "Codasip"
"provider.object" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"provider.priority" => 571
"provider.slug" => "codasip"
"published_as_new_at" => 0
"seofeatures" => """
<ul>\r\n
\t<li>32 bit,</li>\r\n
\t<li>3-stage pipeline,</li>\r\n
\t<li>32 registers</li>\r\n
</ul>
"""
"seofeatures_cn" => ""
"shortdescription" => "32 Bit - Embedded RISC-V Processor Core"
"shortdescription_cn" => ""
"slug" => "32-bit-embedded-risc-v-processor-core"
"sortable_id" => 15584
"taxo0" => array:1 [
0 => 1
]
"taxo1" => array:1 [
0 => 9
]
"taxo2" => array:1 [
0 => 99
]
"taxo3" => array:1 [
0 => 643
]
"taxo4" => []
"taxo5" => []
"taxo6" => []
"taxo7" => []
"taxo8" => []
"text_high_priority" => "Codasip L31(F) 32 Bit - Embedded RISC-V Processor Core"
"text_low_priority" => """
The L31(F) is a small efficient 32-bit embedded RISC-V processor aimed at systems with more modest processing requirements. core has 3-stage pipeline and 32 general-purpose registers.\r\n
The includes optional L1 data instruction caches TCM 8 or 16 PMP regions an interrupt controller Debug module optionally PC trace.\r\n
Like all Codasip cores it possible to create custom instructions using Studio extend the L31 generate corresponding hardware software development kits.\r\n
\r\n
\r\n
\t32-bit core\r\n
\tAvailable in two versions:\r\n
\t\r\n
\t\tRV32IMC\r\n
\t\tRV32IMCF\r\n
\t\r\n
\t\r\n
\t32 general purpose registers\r\n
\tEither parallel multiplier\r\n
\t3-stage pipeline\r\n
\tDynamic branch predictor\r\n
\tRISC-V privilege mode support:\r\n
\t\r\n
\t\tMachine User\r\n
\t\r\n
\t\r\n
\tInternal controller\r\n
\t\r\n
\t\tUp 256 sources\r\n
\t\r\n
\t\r\n
\tOptional FPU (L30F)\r\n
\tOptional tightly coupled memories (TCM)\r\n
\tOptional regions\r\n
\tOptional caches\r\n
\tStandard CLINT\r\n
\t\r\n
\t\tUp sources\r\n
\t\r\n
\t\r\n
\tWakeup controller\r\n
\tNMI\r\n
\tOn-chip debugger\r\n
\t\r\n
\t\tRISC-V module\r\n
\t\r\n
\t\r\n
\t2/4 pin JTAG\r\n
\t2-8 breakpoints/watchpoints\r\n
"""
"text_medium_priority" => "Processor RISC-V RISCV Microcontroller"
"updated_at" => 1724273456
]
"highlight" => array:2 [
"text_high_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> L31(F) 32 Bit - Embedded RISC-V Processor Core"
]
"text_low_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\r\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"highlights" => array:2 [
0 => array:3 [
"field" => "text_high_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> L31(F) 32 Bit - Embedded RISC-V Processor Core"
]
1 => array:3 [
"field" => "text_low_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\r\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"text_match" => 610246614239412226
"text_match_info" => array:7 [
"best_field_score" => "1108091338752"
"best_field_weight" => 15
"fields_matched" => 2
"num_tokens_dropped" => 0
"score" => "610246614239412226"
"tokens_matched" => 1
"typo_prefix_score" => 0
]
]
2 => array:5 [
"document" => array:48 [
"asic.foundry" => []
"asic.foundry_node" => []
"asic.foundry_node_process" => []
"asic.node" => []
"asic.node_foundry" => []
"blockdiagram" => "/upload/catalog/product/blockdiagram/15583/icon_32-bit-compact-risc-v-processor-core-66bb80167f6eb.png.webp"
"category.id" => array:1 [
0 => 643
]
"category.name" => array:1 [
0 => "RISC-V Processor IP"
]
"category.slug" => []
"created_at" => 1645714199
"id" => "15583"
"keyfeatures" => """
<ul>\r\n
\t<li>32-bit RISC-V core</li>\r\n
\t<li>RV32EMC instruction set</li>\r\n
\t<li>16 general purpose registers</li>\r\n
\t<li>Either small sequential multiplier</li>\r\n
\t<li>3-stage pipeline</li>\r\n
\t<li>RISC-V privilege mode support:\r\n
\t<ul>\r\n
\t\t<li>Machine</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Standard RISC-V CLINT\r\n
\t<ul>\r\n
\t\t<li>Up to 256 sources</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Wakeup interrupt controller</li>\r\n
\t<li>NMI</li>\r\n
\t<li>On-chip debugger\r\n
\t<ul>\r\n
\t\t<li>RISC-V Debug module</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>2/4 pin JTAG</li>\r\n
\t<li>2-8 breakpoints/watchpoints</li>\r\n
</ul>
"""
"keyfeatures_cn" => ""
"keywords" => "Processor, RISC-V, RISCV, Microcontroller"
"logo" => "codasip23-66bb478fde085.webp"
"logo2" => "codasip23-66bb478fde085.webp"
"name" => "asic.node"
"overview" => """
<p>The L11 is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requirements. The core has a 3-stage pipeline and with 16 general purpose registers.<br />\r\n
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.<br />\r\n
Like with all Codasip RISC-V cores, it is possible to create custom instructions using Codasip Studio to extend the L10 and to generate corresponding hardware and software development kits.<br />\r\n
</p>
"""
"overview_cn" => ""
"partnumber" => "Codasip L11"
"priority" => 91
"priority_taxo" => 1
"productTypes" => array:1 [
0 => "sip"
]
"provider.id" => 294
"provider.name" => "Codasip"
"provider.object" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"provider.priority" => 571
"provider.slug" => "codasip"
"published_as_new_at" => 0
"seofeatures" => """
<ul>\r\n
\t<li>32-bit RISC-V core</li>\r\n
\t<li>RV32EMC instruction set</li>\r\n
\t<li>16 general purpose registers</li>\r\n
</ul>
"""
"seofeatures_cn" => ""
"shortdescription" => "32 bit - Compact RISC-V Processor Core"
"shortdescription_cn" => ""
"slug" => "32-bit-compact-risc-v-processor-core"
"sortable_id" => 15583
"taxo0" => array:1 [
0 => 1
]
"taxo1" => array:1 [
0 => 9
]
"taxo2" => array:1 [
0 => 99
]
"taxo3" => array:1 [
0 => 643
]
"taxo4" => []
"taxo5" => []
"taxo6" => []
"taxo7" => []
"taxo8" => []
"text_high_priority" => "Codasip L11 32 bit - Compact RISC-V Processor Core"
"text_low_priority" => """
The L11 is a small efficient 32-bit embedded RISC-V processor aimed at systems with more modest processing requirements. core has 3-stage pipeline and 16 general purpose registers.\r\n
The includes optional L1 data instruction caches TCM 8 or PMP regions an interrupt controller Debug module optionally PC trace.\r\n
Like all Codasip cores it possible to create custom instructions using Studio extend the L10 generate corresponding hardware software development kits.\r\n
\r\n
\t32-bit core\r\n
\tRV32EMC set\r\n
\t16 registers\r\n
\tEither sequential multiplier\r\n
\t3-stage pipeline\r\n
\tRISC-V privilege mode support:\r\n
\t\r\n
\t\tMachine\r\n
\t\r\n
\t\r\n
\tStandard CLINT\r\n
\t\r\n
\t\tUp 256 sources\r\n
\t\r\n
\t\r\n
\tWakeup controller\r\n
\tNMI\r\n
\tOn-chip debugger\r\n
\t\r\n
\t\tRISC-V module\r\n
\t\r\n
\t\r\n
\t2/4 pin JTAG\r\n
\t2-8 breakpoints/watchpoints\r\n
"""
"text_medium_priority" => "Processor RISC-V RISCV Microcontroller"
"updated_at" => 1724329853
]
"highlight" => array:2 [
"text_high_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> L11 32 bit - Compact RISC-V Processor Core"
]
"text_low_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\r\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"highlights" => array:2 [
0 => array:3 [
"field" => "text_high_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> L11 32 bit - Compact RISC-V Processor Core"
]
1 => array:3 [
"field" => "text_low_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\r\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"text_match" => 610246614239412226
"text_match_info" => array:7 [
"best_field_score" => "1108091338752"
"best_field_weight" => 15
"fields_matched" => 2
"num_tokens_dropped" => 0
"score" => "610246614239412226"
"tokens_matched" => 1
"typo_prefix_score" => 0
]
]
3 => array:5 [
"document" => array:48 [
"asic.foundry" => []
"asic.foundry_node" => []
"asic.foundry_node_process" => []
"asic.node" => []
"asic.node_foundry" => []
"blockdiagram" => "/upload/catalog/product/blockdiagram/14641/icon_compact-risc-v-processor-32-bit-3-stage-pipeline-32-registers-66bb791106370.png.webp"
"category.id" => array:1 [
0 => 643
]
"category.name" => array:1 [
0 => "RISC-V Processor IP"
]
"category.slug" => []
"created_at" => 1614788957
"id" => "14641"
"keyfeatures" => """
<ul>\r\n
\t<li>32-bit RISC-V core</li>\r\n
\t<li>Available in two versions:\r\n
\t<ul>\r\n
\t\t<li>RV32IMC</li>\r\n
\t\t<li>RV32IMCF</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>32 general purpose registers</li>\r\n
\t<li>Either parallel multiplier</li>\r\n
\t<li>3-stage pipeline</li>\r\n
\t<li>Dynamic branch predictor</li>\r\n
\t<li>RISC-V privilege mode support:\r\n
\t<ul>\r\n
\t\t<li>Machine, User</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Internal interrupt controller\r\n
\t<ul>\r\n
\t\t<li>Up to 256 sources</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Optional FPU (L30F)</li>\r\n
\t<li>Optional instruction and data tightly coupled memories (TCM)</li>\r\n
\t<li>Optional 8 or 16 PMP regions</li>\r\n
\t<li>Optional L1 data and instruction caches</li>\r\n
\t<li>Standard RISC-V CLINT\r\n
\t<ul>\r\n
\t\t<li>Up to 256 sources</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Wakeup interrupt controller</li>\r\n
\t<li>NMI</li>\r\n
\t<li>On-chip debugger\r\n
\t<ul>\r\n
\t\t<li>RISC-V Debug module</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>2/4 pin JTAG</li>\r\n
\t<li>2-8 breakpoints/watchpoints</li>\r\n
</ul>
"""
"keyfeatures_cn" => ""
"keywords" => "Processor, RISC-V, RISCV, Microcontroller"
"logo" => "codasip23-66bb478fde085.webp"
"logo2" => "codasip23-66bb478fde085.webp"
"name" => "asic.node"
"overview" => """
<p>The L30(F) is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requirements. The core has a 3-stage pipeline and has 32 general-purpose registers.<br />\r\n
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.<br />\r\n
Like with all Codasip RISC-V cores, it is possible to create custom instructions using Codasip Studio to extend the L30 and to generate corresponding hardware and software development kits.<br />\r\n
</p>
"""
"overview_cn" => ""
"partnumber" => "Codasip L30(F)"
"priority" => 1
"priority_taxo" => 1
"productTypes" => array:1 [
0 => "sip"
]
"provider.id" => 294
"provider.name" => "Codasip"
"provider.object" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"provider.priority" => 571
"provider.slug" => "codasip"
"published_as_new_at" => 0
"seofeatures" => """
<ul>\r\n
\t<li>32-bit RISC-V core</li>\r\n
\t<li>Available in two versions:</li>\r\n
\t<li>32 general purpose registers</li>\r\n
\t<li>Either parallel multiplier</li>\r\n
</ul>
"""
"seofeatures_cn" => ""
"shortdescription" => "Compact RISC-V Processor - 32 bit, 3-stage pipeline, 32 registers"
"shortdescription_cn" => ""
"slug" => "compact-risc-v-processor-32-bit-3-stage-pipeline-32-registers"
"sortable_id" => 14641
"taxo0" => array:1 [
0 => 1
]
"taxo1" => array:1 [
0 => 9
]
"taxo2" => array:1 [
0 => 99
]
"taxo3" => array:1 [
0 => 643
]
"taxo4" => []
"taxo5" => []
"taxo6" => []
"taxo7" => []
"taxo8" => []
"text_high_priority" => "Codasip L30(F) Compact RISC-V Processor - 32 bit 3-stage pipeline registers"
"text_low_priority" => """
The L30(F) is a small efficient 32-bit embedded RISC-V processor aimed at systems with more modest processing requirements. core has 3-stage pipeline and 32 general-purpose registers.\r\n
The includes optional L1 data instruction caches TCM 8 or 16 PMP regions an interrupt controller Debug module optionally PC trace.\r\n
Like all Codasip cores it possible to create custom instructions using Studio extend the L30 generate corresponding hardware software development kits.\r\n
\r\n
\t32-bit core\r\n
\tAvailable in two versions:\r\n
\t\r\n
\t\tRV32IMC\r\n
\t\tRV32IMCF\r\n
\t\r\n
\t\r\n
\t32 general purpose registers\r\n
\tEither parallel multiplier\r\n
\t3-stage pipeline\r\n
\tDynamic branch predictor\r\n
\tRISC-V privilege mode support:\r\n
\t\r\n
\t\tMachine User\r\n
\t\r\n
\t\r\n
\tInternal controller\r\n
\t\r\n
\t\tUp 256 sources\r\n
\t\r\n
\t\r\n
\tOptional FPU (L30F)\r\n
\tOptional tightly coupled memories (TCM)\r\n
\tOptional regions\r\n
\tOptional caches\r\n
\tStandard CLINT\r\n
\t\r\n
\t\tUp sources\r\n
\t\r\n
\t\r\n
\tWakeup controller\r\n
\tNMI\r\n
\tOn-chip debugger\r\n
\t\r\n
\t\tRISC-V module\r\n
\t\r\n
\t\r\n
\t2/4 pin JTAG\r\n
\t2-8 breakpoints/watchpoints\r\n
"""
"text_medium_priority" => "Processor RISC-V RISCV Microcontroller"
"updated_at" => 1724274361
]
"highlight" => array:2 [
"text_high_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> L30(F) Compact RISC-V Processor - 32 bit 3-stage pipeline registers"
]
"text_low_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\r\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"highlights" => array:2 [
0 => array:3 [
"field" => "text_high_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> L30(F) Compact RISC-V Processor - 32 bit 3-stage pipeline registers"
]
1 => array:3 [
"field" => "text_low_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\r\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"text_match" => 610246614239412226
"text_match_info" => array:7 [
"best_field_score" => "1108091338752"
"best_field_weight" => 15
"fields_matched" => 2
"num_tokens_dropped" => 0
"score" => "610246614239412226"
"tokens_matched" => 1
"typo_prefix_score" => 0
]
]
4 => array:5 [
"document" => array:48 [
"asic.foundry" => []
"asic.foundry_node" => []
"asic.foundry_node_process" => []
"asic.node" => []
"asic.node_foundry" => []
"blockdiagram" => "/upload/catalog/product/blockdiagram/14236/icon_64-bit-risc-v-application-processor-core-66bb760b9ef28.png.webp"
"category.id" => array:1 [
0 => 643
]
"category.name" => array:1 [
0 => "RISC-V Processor IP"
]
"category.slug" => []
"created_at" => 1607105972
"id" => "14236"
"keyfeatures" => "<ul><li>64-bit RISC-V core</li><ul><li> RV64GC (GC=IMAFDC)</li></ul><li>Linux capable</li><li>In-order 7-stage pipeline</li><li>RISC-V mode support:</li><ul><li> Machine</li><li> Supervisor</li><li> User</li></ul><li>Internal interrupt controller</li><ul><li> Up to 256 sources</li></ul><li>Dynamic jump prediction</li><li>Optional FPU</li><li>Integrated L1 data and instruction caches</li><li>L2 cache coherence for up to 4 cores</li><li>MMU</li><li>On-chip debugger</li><ul><li> JTAG and RISC-V Debug module</li></ul><li>>1GHz clock in 22 nm</li></ul>"
"keyfeatures_cn" => ""
"keywords" => "RISC-V,RISCV,64-bit,Linux"
"logo" => "codasip23-66bb478fde085.webp"
"logo2" => "codasip23-66bb478fde085.webp"
"name" => "asic.node"
"overview" => """
The A70 is a powerful 64-bit RISC-V application processor aimed at systems running Linux. The core has an in-order 7-stage pipeline enabling greater than 1 GHz frequencies in 22nm HPC. <br />\n
The core includes integrated L1 data and instruction caches, an interrupt controller and RISC-V Debug module optionally with PC trace.<br />\n
Like all Codasip RISC-V cores it is possible to create custom instructions using Codasip Studio to extend the ISA and to generate corresponding hardware and software development kits.<br />\n
"""
"overview_cn" => ""
"partnumber" => "Codasip A70-MP"
"priority" => 41
"priority_taxo" => 1
"productTypes" => array:1 [
0 => "sip"
]
"provider.id" => 294
"provider.name" => "Codasip"
"provider.object" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"provider.priority" => 571
"provider.slug" => "codasip"
"published_as_new_at" => 0
"seofeatures" => "<ul><li>High computational throughput with 7-stage pipeline and branch predictor</li><li>Support for RISC-V single and double precision FPU</li></ul>"
"seofeatures_cn" => ""
"shortdescription" => "64-bit RISC-V Application Processor Core"
"shortdescription_cn" => ""
"slug" => "64-bit-risc-v-application-processor-core-1"
"sortable_id" => 14236
"taxo0" => array:1 [
0 => 1
]
"taxo1" => array:1 [
0 => 9
]
"taxo2" => array:1 [
0 => 99
]
"taxo3" => array:1 [
0 => 643
]
"taxo4" => []
"taxo5" => []
"taxo6" => []
"taxo7" => []
"taxo8" => []
"text_high_priority" => "Codasip A70-MP 64-bit RISC-V Application Processor Core"
"text_low_priority" => """
The A70 is a powerful 64-bit RISC-V application processor aimed at systems running Linux. core has an in-order 7-stage pipeline enabling greater than 1 GHz frequencies in 22nm HPC. \n
The includes integrated L1 data and instruction caches interrupt controller Debug module optionally with PC trace.\n
Like all Codasip cores it possible to create custom instructions using Studio extend the ISA generate corresponding hardware software development kits.\n
RV64GC (GC=IMAFDC)Linux capableIn-order pipelineRISC-V mode support: Machine Supervisor UserInternal Up 256 sourcesDynamic jump predictionOptional FPUIntegrated cachesL2 cache coherence for up 4 coresMMUOn-chip debugger JTAG module>1GHz clock 22 nm
"""
"text_medium_priority" => "RISC-V RISCV 64-bit Linux "
"updated_at" => 1695309751
]
"highlight" => array:2 [
"text_high_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> A70-MP 64-bit RISC-V Application Processor Core"
]
"text_low_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"highlights" => array:2 [
0 => array:3 [
"field" => "text_high_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> A70-MP 64-bit RISC-V Application Processor Core"
]
1 => array:3 [
"field" => "text_low_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"text_match" => 610246614239412226
"text_match_info" => array:7 [
"best_field_score" => "1108091338752"
"best_field_weight" => 15
"fields_matched" => 2
"num_tokens_dropped" => 0
"score" => "610246614239412226"
"tokens_matched" => 1
"typo_prefix_score" => 0
]
]
5 => array:5 [
"document" => array:48 [
"asic.foundry" => []
"asic.foundry_node" => []
"asic.foundry_node_process" => []
"asic.node" => []
"asic.node_foundry" => []
"blockdiagram" => "/upload/catalog/product/blockdiagram/14235/icon_64-bit-risc-v-application-processor-core-66bb76083e20a.png.webp"
"category.id" => array:1 [
0 => 643
]
"category.name" => array:1 [
0 => "RISC-V Processor IP"
]
"category.slug" => []
"created_at" => 1607105564
"id" => "14235"
"keyfeatures" => "<ul><li>64-bit RISC-V core</li><ul><li> RV64GC (GC=IMAFDC)</li></ul><li>Linux capable</li><li>In-order 7-stage pipeline</li><li>RISC-V mode support:</li><ul><li> Machine</li><li> Supervisor</li><li> User</li></ul><li>Internal interrupt controller</li><ul><li> Up to 256 sources</li></ul><li>Dynamic jump prediction</li><li>Optional FPU</li><li>Integrated L1 data and instruction caches</li><li>MMU</li><li>On-chip debugger</li><ul><li> JTAG and RISC-V Debug module</li></ul><li>>1GHz clock in 22 nm</li></ul>"
"keyfeatures_cn" => ""
"keywords" => "RISC-V,RISCV,64-bit,Linux"
"logo" => "codasip23-66bb478fde085.webp"
"logo2" => "codasip23-66bb478fde085.webp"
"name" => "asic.node"
"overview" => """
The A70 is a powerful 64-bit RISC-V application processor aimed at systems running Linux. The core has an in-order 7-stage pipeline enabling greater than 1 GHz frequencies in 22nm HPC. <br />\n
The core includes integrated L1 data and instruction caches, an interrupt controller and RISC-V Debug module optionally with PC trace.<br />\n
Like all Codasip RISC-V cores it is possible to create custom instructions using Codasip Studio to extend the ISA and to generate corresponding hardware and software development kits.<br />\n
Tensor Flow Lite Micro is supported<br />\n
"""
"overview_cn" => ""
"partnumber" => "Codasip A70"
"priority" => 101
"priority_taxo" => 1
"productTypes" => array:1 [
0 => "sip"
]
"provider.id" => 294
"provider.name" => "Codasip"
"provider.object" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"provider.priority" => 571
"provider.slug" => "codasip"
"published_as_new_at" => 0
"seofeatures" => "<ul><li>64-bit RISC-V core</li><li>Linux capable</li><li>In-order 7-stage pipeline</li></ul>"
"seofeatures_cn" => ""
"shortdescription" => "64-bit RISC-V Application Processor Core"
"shortdescription_cn" => ""
"slug" => "64-bit-risc-v-application-processor-core"
"sortable_id" => 14235
"taxo0" => array:1 [
0 => 1
]
"taxo1" => array:1 [
0 => 9
]
"taxo2" => array:1 [
0 => 99
]
"taxo3" => array:1 [
0 => 643
]
"taxo4" => []
"taxo5" => []
"taxo6" => []
"taxo7" => []
"taxo8" => []
"text_high_priority" => "Codasip A70 64-bit RISC-V Application Processor Core"
"text_low_priority" => """
The A70 is a powerful 64-bit RISC-V application processor aimed at systems running Linux. core has an in-order 7-stage pipeline enabling greater than 1 GHz frequencies in 22nm HPC. \n
The includes integrated L1 data and instruction caches interrupt controller Debug module optionally with PC trace.\n
Like all Codasip cores it possible to create custom instructions using Studio extend the ISA generate corresponding hardware software development kits.\n
Tensor Flow Lite Micro supported\n
RV64GC (GC=IMAFDC)Linux capableIn-order pipelineRISC-V mode support: Machine Supervisor UserInternal Up 256 sourcesDynamic jump predictionOptional FPUIntegrated cachesMMUOn-chip debugger JTAG module>1GHz clock 22 nm
"""
"text_medium_priority" => "RISC-V RISCV 64-bit Linux "
"updated_at" => 1695309729
]
"highlight" => array:2 [
"text_high_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> A70 64-bit RISC-V Application Processor Core"
]
"text_low_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"highlights" => array:2 [
0 => array:3 [
"field" => "text_high_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> A70 64-bit RISC-V Application Processor Core"
]
1 => array:3 [
"field" => "text_low_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"text_match" => 610246614239412226
"text_match_info" => array:7 [
"best_field_score" => "1108091338752"
"best_field_weight" => 15
"fields_matched" => 2
"num_tokens_dropped" => 0
"score" => "610246614239412226"
"tokens_matched" => 1
"typo_prefix_score" => 0
]
]
6 => array:5 [
"document" => array:48 [
"asic.foundry" => []
"asic.foundry_node" => []
"asic.foundry_node_process" => []
"asic.node" => []
"asic.node_foundry" => []
"blockdiagram" => "/upload/catalog/product/blockdiagram/13700/icon_processor-development-toolset-66bb724ab758f.png.webp"
"category.id" => array:1 [
0 => 643
]
"category.name" => array:1 [
0 => "RISC-V Processor IP"
]
"category.slug" => []
"created_at" => 1585330653
"id" => "13700"
"keyfeatures" => """
<ul>\r\n
\t<li>A unified development model describing the processor in a single CodAL description</li>\r\n
\t<li>High performance processor synthesis</li>\r\n
\t<li>Complete UVM verification environment</li>\r\n
\t<li>Advanced profiling and analysis</li>\r\n
\t<li>Compatible with Codasip RISC-V cores</li>\r\n
</ul>
"""
"keyfeatures_cn" => ""
"keywords" => "Processor, toolset, EDA, RISC-V, RISCV, ISS, SDK, HDK, UVM, CodAL, co-simulation,ASIP,domain-specific design"
"logo" => "codasip23-66bb478fde085.webp"
"logo2" => "codasip23-66bb478fde085.webp"
"name" => "asic.node"
"overview" => """
<p>Codasip Studio is a complete set of Electronic Design Automation (EDA) tools for processor design and customization. The level of automation is unmatched on the market, and produces fast and efficient results.<br />\r\n
<br />\r\n
Our approach at Codasip is to automate the development of processor cores by using a high-level description in the CodAL processor description language and generating the design implementation, verification environment, virtual system prototype, and a complete software toolchain using Codasip Studio.<br />\r\n
<br />\r\n
In addition to its design capabilities, Codasip Studio includes powerful multiprocessor programming, debugging and profiling features, enabling the development of complex processor designs with ease.<br />\r\n
<br />\r\n
Codasip Studio is built upon open standards and software including Eclipse, LLVM, Verilog, SystemVerilog, and UVM.</p>
"""
"overview_cn" => ""
"partnumber" => "Codasip Studio"
"priority" => 91
"priority_taxo" => 1
"productTypes" => array:1 [
0 => "sip"
]
"provider.id" => 294
"provider.name" => "Codasip"
"provider.object" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"provider.priority" => 571
"provider.slug" => "codasip"
"published_as_new_at" => 0
"seofeatures" => """
<ul>\r\n
\t<li>A unified development model describing the processor in a single CodAL description</li>\r\n
\t<li>High performance processor synthesis</li>\r\n
\t<li>Complete UVM verification environment</li>\r\n
\t<li>Advanced profiling and analysis</li>\r\n
</ul>
"""
"seofeatures_cn" => ""
"shortdescription" => "Processor Development Toolset"
"shortdescription_cn" => ""
"slug" => "processor-development-toolset"
"sortable_id" => 13700
"taxo0" => array:1 [
0 => 1
]
"taxo1" => array:1 [
0 => 9
]
"taxo2" => array:1 [
0 => 99
]
"taxo3" => array:1 [
0 => 643
]
"taxo4" => []
"taxo5" => []
"taxo6" => []
"taxo7" => []
"taxo8" => []
"text_high_priority" => "Codasip Studio Processor Development Toolset"
"text_low_priority" => """
Codasip Studio is a complete set of Electronic Design Automation (EDA) tools for processor design and customization. The level automation unmatched on the market produces fast efficient results.\r\n
\r\n
Our approach at to automate development cores by using high-level description in CodAL language generating implementation verification environment virtual system prototype software toolchain Studio.\r\n
\r\n
In addition its capabilities includes powerful multiprocessor programming debugging profiling features enabling complex designs with ease.\r\n
\r\n
Codasip built upon open standards including Eclipse LLVM Verilog SystemVerilog UVM. \r\n
\tA unified model describing single description\r\n
\tHigh performance synthesis\r\n
\tComplete UVM environment\r\n
\tAdvanced analysis\r\n
\tCompatible RISC-V cores\r\n
"""
"text_medium_priority" => "Processor toolset EDA RISC-V RISCV ISS SDK HDK UVM CodAL co-simulation ASIP domain-specific design"
"updated_at" => 1724273514
]
"highlight" => array:2 [
"text_high_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> Studio Processor Development Toolset"
]
"text_low_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> Studio is a complete"
]
]
"highlights" => array:2 [
0 => array:3 [
"field" => "text_high_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> Studio Processor Development Toolset"
]
1 => array:3 [
"field" => "text_low_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> Studio is a complete"
]
]
"text_match" => 610246614239412226
"text_match_info" => array:7 [
"best_field_score" => "1108091338752"
"best_field_weight" => 15
"fields_matched" => 2
"num_tokens_dropped" => 0
"score" => "610246614239412226"
"tokens_matched" => 1
"typo_prefix_score" => 0
]
]
7 => array:5 [
"document" => array:48 [
"asic.foundry" => []
"asic.foundry_node" => []
"asic.foundry_node_process" => []
"asic.node" => []
"asic.node_foundry" => []
"blockdiagram" => "/upload/catalog/product/blockdiagram/11810/icon_compact-efficient-64-bit-risc-v-processor-with-5-stage-pipeline-66bb6723b03a8.png.webp"
"category.id" => array:1 [
0 => 643
]
"category.name" => array:1 [
0 => "RISC-V Processor IP"
]
"category.slug" => []
"created_at" => 1511859747
"id" => "11810"
"keyfeatures" => "<ul><li>64-bit RISC-V core</li><ul><li> H50X supports RV64IMC</li><li> H50XF supports RV64IMCF</li></ul><li>Fully parallel multiplier</li><li>5-stage pipeline</li><li>Dynamic Branch Predictor</li><li>RISC-V mode support:</li><ul><li> Machine, User</li></ul><li>Internal interrupt controller</li><ul><li> Up to 256 sources</li></ul><li>FPU (H50F)</li><li>Optional instruction and data tightly coupled memories (TCM)</li><li>Optional 8 or 16 PMP regions</li><li>Optional L1 data and instruction caches</li><li>On-chip debugger</li><ul><li> JTAG and RISC-V Debug module</li></ul></ul>"
"keyfeatures_cn" => ""
"keywords" => "RISC-V, RISCV, Processor"
"logo" => "codasip23-66bb478fde085.webp"
"logo2" => "codasip23-66bb478fde085.webp"
"name" => "asic.node"
"overview" => """
The H50 is an entry level, compact, efficient 64-bit embedded RISC-V processor aimed at embedded systems requiring a large address space. The core has a 5-stage pipeline and is offered in two versions. <br />\n
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.<br />\n
Like with all Codasip RISC-V cores, it is possible to create custom instructions using Codasip Studio to extend the H50 and to generate corresponding hardware and software development kits.<br />\n
"""
"overview_cn" => ""
"partnumber" => "Codasip H50(F)"
"priority" => 1
"priority_taxo" => 1
"productTypes" => array:1 [
0 => "sip"
]
"provider.id" => 294
"provider.name" => "Codasip"
"provider.object" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"provider.priority" => 571
"provider.slug" => "codasip"
"published_as_new_at" => 0
"seofeatures" => "<ul><li>Support for RV32IM</li><li>5-stage pipeline</li><li>Thirty-two 64-bit general purpose registers</li></ul>"
"seofeatures_cn" => ""
"shortdescription" => "Compact, efficient 64-bit RISC-V processor with 5-stage pipeline"
"shortdescription_cn" => ""
"slug" => "compact-efficient-64-bit-risc-v-processor-with-5-stage-pipeline"
"sortable_id" => 11810
"taxo0" => array:1 [
0 => 1
]
"taxo1" => array:1 [
0 => 9
]
"taxo2" => array:1 [
0 => 99
]
"taxo3" => array:1 [
0 => 643
]
"taxo4" => []
"taxo5" => []
"taxo6" => []
"taxo7" => []
"taxo8" => []
"text_high_priority" => "Codasip H50(F) Compact efficient 64-bit RISC-V processor with 5-stage pipeline"
"text_low_priority" => """
The H50 is an entry level compact efficient 64-bit embedded RISC-V processor aimed at systems requiring a large address space. core has 5-stage pipeline and offered in two versions. \n
The includes optional L1 data instruction caches TCM 8 or 16 PMP regions interrupt controller Debug module optionally with PC trace.\n
Like all Codasip cores it possible to create custom instructions using Studio extend the generate corresponding hardware software development kits.\n
H50X supports RV64IMC H50XF RV64IMCFFully parallel multiplier5-stage pipelineDynamic Branch PredictorRISC-V mode support: Machine UserInternal Up 256 sourcesFPU (H50F)Optional tightly coupled memories (TCM)Optional regionsOptional cachesOn-chip debugger JTAG
"""
"text_medium_priority" => "RISC-V RISCV Processor"
"updated_at" => 1694450608
]
"highlight" => array:2 [
"text_high_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> H50(F) Compact efficient 64-bit RISC-V processor with 5-stage pipeline"
]
"text_low_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"highlights" => array:2 [
0 => array:3 [
"field" => "text_high_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> H50(F) Compact efficient 64-bit RISC-V processor with 5-stage pipeline"
]
1 => array:3 [
"field" => "text_low_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"text_match" => 610246614239412226
"text_match_info" => array:7 [
"best_field_score" => "1108091338752"
"best_field_weight" => 15
"fields_matched" => 2
"num_tokens_dropped" => 0
"score" => "610246614239412226"
"tokens_matched" => 1
"typo_prefix_score" => 0
]
]
8 => array:5 [
"document" => array:48 [
"asic.foundry" => []
"asic.foundry_node" => []
"asic.foundry_node_process" => []
"asic.node" => []
"asic.node_foundry" => []
"blockdiagram" => "/upload/catalog/product/blockdiagram/9729/icon_risc-v-processor-32-bit-5-stage-pipeline-66bb5e01b1d4d.png.webp"
"category.id" => array:1 [
0 => 643
]
"category.name" => array:1 [
0 => "RISC-V Processor IP"
]
"category.slug" => []
"created_at" => 1477431465
"id" => "9729"
"keyfeatures" => """
<ul>\r\n
\t<li>32-bit RISC-V core\r\n
\t<ul>\r\n
\t\t<li>The L50 supports the RV32IMC ISA</li>\r\n
\t\t<li>The L50F supports the RV32IMCF ISA</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Fully parallel multiplier</li>\r\n
\t<li>5-stage pipeline</li>\r\n
\t<li>Dynamic Branch Predictor</li>\r\n
\t<li>RISC-V privilege mode support:\r\n
\t<ul>\r\n
\t\t<li>Machine, User</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Internal interrupt controller\r\n
\t<ul>\r\n
\t\t<li>Up to 256 sources</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Optional FPU (L50F)</li>\r\n
\t<li>Optional instruction and data tightly coupled memories (TCM)</li>\r\n
\t<li>Optional 8 or 16 PMP regions</li>\r\n
\t<li>Optional L1 data and instruction caches</li>\r\n
\t<li>On-chip debugger\r\n
\t<ul>\r\n
\t\t<li>JTAG and RISC-V Debug module</li>\r\n
\t</ul>\r\n
\t</li>\r\n
</ul>
"""
"keyfeatures_cn" => ""
"keywords" => "RISC-V, RISCV, Processor"
"logo" => "codasip23-66bb478fde085.webp"
"logo2" => "codasip23-66bb478fde085.webp"
"name" => "asic.node"
"overview" => """
<p>The L50(F) is a medium-sized, efficient 32-bit embedded RISC-V processor aimed at embedded systems with mid-range processing requirements. The core has a 5-stage pipeline. The L50F has a floating point unit.<br />\r\n
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.<br />\r\n
Like with all Codasip RISC-V cores, it is possible to create custom instructions using Codasip Studio to extend the L50 or L50F and to generate corresponding hardware and software development kits.</p>
"""
"overview_cn" => ""
"partnumber" => "Codasip L50(F)"
"priority" => 1
"priority_taxo" => 1
"productTypes" => array:1 [
0 => "sip"
]
"provider.id" => 294
"provider.name" => "Codasip"
"provider.object" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"provider.priority" => 571
"provider.slug" => "codasip"
"published_as_new_at" => 0
"seofeatures" => """
<ul>\r\n
\t<li>Support for RV32IM/RV64IM</li>\r\n
\t<li>5-stage pipeline</li>\r\n
\t<li>32 or 64bit general purpose registers</li>\r\n
</ul>
"""
"seofeatures_cn" => ""
"shortdescription" => "RISC-V processor - 32 bit, 5-stage pipeline"
"shortdescription_cn" => ""
"slug" => "risc-v-processor-32-bit-5-stage-pipeline"
"sortable_id" => 9729
"taxo0" => array:1 [
0 => 1
]
"taxo1" => array:1 [
0 => 9
]
"taxo2" => array:1 [
0 => 99
]
"taxo3" => array:1 [
0 => 643
]
"taxo4" => []
"taxo5" => []
"taxo6" => []
"taxo7" => []
"taxo8" => []
"text_high_priority" => "Codasip L50(F) RISC-V processor - 32 bit 5-stage pipeline"
"text_low_priority" => """
The L50(F) is a medium-sized efficient 32-bit embedded RISC-V processor aimed at systems with mid-range processing requirements. core has 5-stage pipeline. L50F floating point unit.\r\n
The includes optional L1 data and instruction caches TCM 8 or 16 PMP regions an interrupt controller Debug module optionally PC trace.\r\n
Like all Codasip cores it possible to create custom instructions using Studio extend the L50 generate corresponding hardware software development kits. \r\n
\t32-bit core\r\n
\t\r\n
\t\tThe supports RV32IMC ISA\r\n
\t\tThe RV32IMCF ISA\r\n
\t\r\n
\t\r\n
\tFully parallel multiplier\r\n
\t5-stage pipeline\r\n
\tDynamic Branch Predictor\r\n
\tRISC-V privilege mode support:\r\n
\t\r\n
\t\tMachine User\r\n
\t\r\n
\t\r\n
\tInternal controller\r\n
\t\r\n
\t\tUp 256 sources\r\n
\t\r\n
\t\r\n
\tOptional FPU (L50F)\r\n
\tOptional tightly coupled memories (TCM)\r\n
\tOptional regions\r\n
\tOptional caches\r\n
\tOn-chip debugger\r\n
\t\r\n
\t\tJTAG module\r\n
\t\r\n
\t\r\n
"""
"text_medium_priority" => "RISC-V RISCV Processor"
"updated_at" => 1724273763
]
"highlight" => array:2 [
"text_high_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> L50(F) RISC-V processor - 32 bit 5-stage pipeline"
]
"text_low_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\r\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"highlights" => array:2 [
0 => array:3 [
"field" => "text_high_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> L50(F) RISC-V processor - 32 bit 5-stage pipeline"
]
1 => array:3 [
"field" => "text_low_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\r\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"text_match" => 610246614239412226
"text_match_info" => array:7 [
"best_field_score" => "1108091338752"
"best_field_weight" => 15
"fields_matched" => 2
"num_tokens_dropped" => 0
"score" => "610246614239412226"
"tokens_matched" => 1
"typo_prefix_score" => 0
]
]
9 => array:5 [
"document" => array:48 [
"asic.foundry" => []
"asic.foundry_node" => []
"asic.foundry_node_process" => []
"asic.node" => []
"asic.node_foundry" => []
"blockdiagram" => "/upload/catalog/product/blockdiagram/18735/icon_picture2-3-674b14421d6b0.png.webp"
"category.id" => array:1 [
0 => 643
]
"category.name" => array:1 [
0 => "RISC-V Processor IP"
]
"category.slug" => []
"created_at" => 1714399022
"id" => "18735"
"keyfeatures" => """
<ul>\r\n
\t<li>Flexible use cases\r\n
\t<ul>\r\n
\t\t<li>Safety Island as a protected enclave of the device providing freedom of interface for the independent execution of safety-related application code. </li>\r\n
\t\t<li>Controller, running the safety-related application code. </li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Proven technology\r\n
\t<ul>\r\n
\t\t<li>Based on the L31 silicon-proven embedded processor </li>\r\n
\t\t<li>State-of-the-art verification scheme brings quality and reliability </li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>State-of-the-art safety and security\r\n
\t<ul>\r\n
\t\t<li>Dual-core lockstep provides a robust and well trusted approach to building high-reliability systems and meeting the stringent safety requirements of critical applications </li>\r\n
\t\t<li>\u{200B}L31AS increases security against certain threat scenarios and can help meet requirements for security certification </li>\r\n
\t</ul>\r\n
\t</li>\r\n
</ul>
"""
"keyfeatures_cn" => ""
"keywords" => "Processor, RISC-V, RISCV, Microcontroller, TuV SuD ISO 26262"
"logo" => "codasip23-66bb478fde085.webp"
"logo2" => "codasip23-66bb478fde085.webp"
"name" => "asic.node"
"overview" => """
<p>The L31AS is a 32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification. Part of our safety and security offering, this embedded processor is ideal either as a Main Controller or a Safety Island in a Functional Safety System.<br />\r\n
<br />\r\n
It includes 2 instances of the L31 in a dual-core lockstep configuration along with Physical Memory Protection as a security feature.<br />\r\n
</p>\r\n
\r\n
<p>L31AS is an in-order, 3-stage, single-issue RISC-V core targeted for automotive and other functional safety applications. It is based on the RV32IMC ISA. It includes physical memory protection. </p>\r\n
\r\n
<p>L31AS features separate Data and Instruction AHB-Lite interfaces, block-level gating in single-core configuration and performance counters. It uses the standard RISC-V debug specification with 4 debug triggers and Debug Memory Interface (DMI) as an APB interface that can be used to interface with external debuggers. </p>\r\n
\r\n
<p><strong>Certified for Functional Safety</strong></p>\r\n
\r\n
<p>The L31AS core is certified by TÜV SÜD according to the requirements set forth in ISO26262 up to ASIL B. It is delivered with a safety pack including a safety manual and a safety case report. </p>\r\n
\r\n
<p><strong>Software development</strong></p>\r\n
\r\n
<p>Using standard AMBA AHB Interface, L31AS can easily be connected to existing systems and interconnects.\u{202F}What is more, L31AS is designed to simplify software development, with essential features to support developers:\u{202F} </p>\r\n
\r\n
<ul>\r\n
\t<li><strong>Debug interface</strong>\u{202F}– using standard RISC-V Debug specification\u{202F}\u{202F} </li>\r\n
\t<li><strong>Instruction-accurate model</strong>\u{202F}–\u{202F}for fast execution of software, before hardware is available\u{202F} </li>\r\n
\t<li><strong>Cycle-accurate model</strong>\u{202F}–\u{202F}for software algorithm optimization, when time constraints require precise execution\u{202F} </li>\r\n
\t<li><strong>Full trace capability</strong>\u{202F}– in the cycle-accurate model, to hunt hard-to-find bugs\u{202F} </li>\r\n
</ul>
"""
"overview_cn" => ""
"partnumber" => "Codasip L31AS"
"priority" => 1
"priority_taxo" => 1
"productTypes" => array:1 [
0 => "sip"
]
"provider.id" => 294
"provider.name" => "Codasip"
"provider.object" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"provider.priority" => 571
"provider.slug" => "codasip"
"published_as_new_at" => 0
"seofeatures" => """
<ul>\r\n
\t<li>Flexible use cases</li>\r\n
\t<li>roven technology</li>\r\n
\t<li>State-of-the-art safety and security\r\n
\t<ul>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<br />\r\n
\t<br />\r\n
\t<br />\r\n
\t \r\n
\t<li> </li>\r\n
</ul>
"""
"seofeatures_cn" => ""
"shortdescription" => "32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification"
"shortdescription_cn" => ""
"slug" => "32-bit-risc-v-embedded-processor-with-tuv-sud-iso-26262-asil-b-certification"
"sortable_id" => 18735
"taxo0" => array:1 [
0 => 1
]
"taxo1" => array:1 [
0 => 9
]
"taxo2" => array:1 [
0 => 99
]
"taxo3" => array:1 [
0 => 643
]
"taxo4" => []
"taxo5" => []
"taxo6" => []
"taxo7" => []
"taxo8" => []
"text_high_priority" => "Codasip L31AS 32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification"
"text_low_priority" => """
The L31AS is a 32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification. Part of our safety and security offering this ideal either as Main Controller or Safety Island in Functional System.\r\n
\r\n
It includes 2 instances the L31 dual-core lockstep configuration along Physical Memory Protection feature.\r\n
\r\n
\r\n
L31AS an in-order 3-stage single-issue core targeted for automotive other functional applications. It based on RV32IMC ISA. physical memory protection. \r\n
\r\n
L31AS features separate Data Instruction AHB-Lite interfaces block-level gating single-core performance counters. uses standard debug specification 4 triggers Debug Interface (DMI) APB interface that can be used to external debuggers. \r\n
\r\n
Certified Safety\r\n
\r\n
The certified by according requirements set forth in ISO26262 up B. delivered pack including manual case report. \r\n
\r\n
Software development\r\n
\r\n
Using AMBA AHB easily connected existing systems interconnects.\u{202F}What more designed simplify software development essential support developers:\u{202F} \r\n
\r\n
\r\n
\tDebug interface\u{202F}– using specification\u{202F}\u{202F} \r\n
\tInstruction-accurate model\u{202F}–\u{202F}for fast execution before hardware available\u{202F} \r\n
\tCycle-accurate algorithm optimization when time constraints require precise execution\u{202F} \r\n
\tFull trace capability\u{202F}– cycle-accurate model hunt hard-to-find bugs\u{202F} \r\n
\r\n
\tFlexible use cases\r\n
\t\r\n
\t\tSafety Island as protected enclave device providing freedom independent safety-related application code. \r\n
\t\tController running code. \r\n
\t\r\n
\t\r\n
\tProven technology\r\n
\t\r\n
\t\tBased silicon-proven embedded processor \r\n
\t\tState-of-the-art verification scheme brings quality reliability \r\n
\t\r\n
\t\r\n
\tState-of-the-art security\r\n
\t\r\n
\t\tDual-core provides robust well trusted approach building high-reliability meeting stringent requirements critical applications \r\n
\t\t\u{200B}L31AS increases against certain threat scenarios help meet certification \r\n
\t\r\n
\t\r\n
"""
"text_medium_priority" => "Processor RISC-V RISCV Microcontroller TuV SuD ISO 26262"
"updated_at" => 1732977234
]
"highlight" => array:1 [
"text_high_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> L31AS 32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification"
]
]
"highlights" => array:1 [
0 => array:3 [
"field" => "text_high_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> L31AS 32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification"
]
]
"text_match" => 610246614239412225
"text_match_info" => array:7 [
"best_field_score" => "1108091338752"
"best_field_weight" => 15
"fields_matched" => 1
"num_tokens_dropped" => 0
"score" => "610246614239412225"
"tokens_matched" => 1
"typo_prefix_score" => 0
]
]
]
"out_of" => 18250
"page" => 1
"request_params" => array:4 [
"collection_name" => "product_semiiphub"
"first_q" => "Codasip"
"per_page" => 10
"q" => "Codasip"
]
"search_cutoff" => false
"search_time_ms" => 1
]
2 => array:8 [
"facet_counts" => array:6 [
0 => array:4 [
"counts" => array:1 [
0 => array:3 [
"count" => 11
"highlighted" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"value" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
]
]
"field_name" => "provider.object"
"sampled" => false
"stats" => array:1 [
"total_values" => 1
]
]
1 => array:4 [
"counts" => []
"field_name" => "asic.foundry"
"sampled" => false
"stats" => array:1 [
"total_values" => 0
]
]
2 => array:4 [
"counts" => []
"field_name" => "asic.foundry_node"
"sampled" => false
"stats" => array:1 [
"total_values" => 0
]
]
3 => array:4 [
"counts" => []
"field_name" => "asic.node_foundry"
"sampled" => false
"stats" => array:1 [
"total_values" => 0
]
]
4 => array:4 [
"counts" => []
"field_name" => "asic.node"
"sampled" => false
"stats" => array:1 [
"total_values" => 0
]
]
5 => array:4 [
"counts" => array:1 [
0 => array:3 [
"count" => 11
"highlighted" => "sip"
"value" => "sip"
]
]
"field_name" => "productTypes"
"sampled" => false
"stats" => array:1 [
"total_values" => 1
]
]
]
"found" => 11
"hits" => array:10 [
0 => array:5 [
"document" => array:48 [
"asic.foundry" => []
"asic.foundry_node" => []
"asic.foundry_node_process" => []
"asic.node" => []
"asic.node_foundry" => []
"blockdiagram" => "/upload/catalog/product/blockdiagram/18819/icon_32-bit-embedded-risc-v-processor-core-66bb99ade2a8e.png.webp"
"category.id" => array:1 [
0 => 643
]
"category.name" => array:1 [
0 => "RISC-V Processor IP"
]
"category.slug" => []
"created_at" => 1723570603
"id" => "18819"
"keyfeatures" => """
<ul>\r\n
\t<li>Best-in-class performance for small-area and low-power applications\r\n
\t<ul>\r\n
\t\t<li>Delivering up to 50% improvements in performance per watt compared to similar cores in the market</li>\r\n
\t\t<li>Smaller and more performant than other RISC-V alternatives</li>\r\n
\t\t<li>Uses RISC-V standard extensions for area and code size reduction for additional power consumption reduction at system level</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Highly configurable and easy and quick to customize and verify\r\n
\t<ul>\r\n
\t\t<li>High-quality pre-verified baseline excellent for further configurations and</li>\r\n
\t\t<li>customization</li>\r\n
\t\t<li>Easy to customize and verify thanks to Codasip Studio Fusion</li>\r\n
\t\t<li>Customization is without risk, because the functionality of the baseline core is guaranteed</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Process compliant with ISO 26262 and ISO 21434\r\n
\t<ul>\r\n
\t\t<li>Developed using HW development process certified by TÜV SÜD</li>\r\n
\t\t<li>Development process certified for functional safety as well as cybersecurity</li>\r\n
\t</ul>\r\n
\t</li>\r\n
</ul>
"""
"keyfeatures_cn" => ""
"keywords" => "RISC-V processor, RISCV processor,RISC-V, RISCV"
"logo" => "codasip23-66bb478fde085.webp"
"logo2" => "codasip23-66bb478fde085.webp"
"name" => "asic.node"
"overview" => """
<p>Codasip® L110 is a 32-bit RISC-V embedded processor, focused on small-area and low-power applications.<br />\r\n
<br />\r\n
The core is highly configurable, allowing different area and performance levels, with optional support for standard RISC-V code size density extension.<br />\r\n
<br />\r\n
It is also fully customizable, and, when used in combination with Codasip Studio, it enables an easy and no-risk way to add custom instructions.</p>
"""
"overview_cn" => ""
"partnumber" => "Codasip L110"
"priority" => 61
"priority_taxo" => 1
"productTypes" => array:1 [
0 => "sip"
]
"provider.id" => 294
"provider.name" => "Codasip"
"provider.object" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"provider.priority" => 571
"provider.slug" => "codasip"
"published_as_new_at" => 0
"seofeatures" => """
<ul>\r\n
\t<li>Best-in-class performance for small-area and low-power applications</li>\r\n
\t<li>Highly configurable and easy and quick to customize and verify</li>\r\n
\t<li>Process compliant with ISO 26262 and ISO 21434</li>\r\n
</ul>
"""
"seofeatures_cn" => ""
"shortdescription" => "32 Bit - Embedded RISC-V Processor Core"
"shortdescription_cn" => ""
"slug" => "32-bit-embedded-risc-v-processor-core-1"
"sortable_id" => 18819
"taxo0" => array:1 [
0 => 1
]
"taxo1" => array:1 [
0 => 9
]
"taxo2" => array:1 [
0 => 99
]
"taxo3" => array:1 [
0 => 643
]
"taxo4" => []
"taxo5" => []
"taxo6" => []
"taxo7" => []
"taxo8" => []
"text_high_priority" => "Codasip L110 32 Bit - Embedded RISC-V Processor Core"
"text_low_priority" => """
Codasip® L110 is a 32-bit RISC-V embedded processor focused on small-area and low-power applications.\r\n
\r\n
The core highly configurable allowing different area performance levels with optional support for standard code size density extension.\r\n
\r\n
It also fully customizable when used in combination Codasip Studio it enables an easy no-risk way to add custom instructions. \r\n
\tBest-in-class applications\r\n
\t\r\n
\t\tDelivering up 50% improvements per watt compared similar cores the market\r\n
\t\tSmaller more performant than other alternatives\r\n
\t\tUses extensions reduction additional power consumption at system level\r\n
\t\r\n
\t\r\n
\tHighly quick customize verify\r\n
\t\r\n
\t\tHigh-quality pre-verified baseline excellent further configurations and\r\n
\t\tcustomization\r\n
\t\tEasy verify thanks Fusion\r\n
\t\tCustomization without risk because functionality of guaranteed\r\n
\t\r\n
\t\r\n
\tProcess compliant ISO 26262 21434\r\n
\t\r\n
\t\tDeveloped using HW development process certified by TÜV SÜD\r\n
\t\tDevelopment functional safety as well cybersecurity\r\n
\t\r\n
\t\r\n
"""
"text_medium_priority" => "RISC-V processor RISCV"
"updated_at" => 1724329863
]
"highlight" => array:2 [
"text_high_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> L110 32 Bit - Embedded RISC-V Processor Core"
]
"text_low_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark>® L110 is a 32-bit"
]
]
"highlights" => array:2 [
0 => array:3 [
"field" => "text_low_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark>® L110 is a 32-bit"
]
1 => array:3 [
"field" => "text_high_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> L110 32 Bit - Embedded RISC-V Processor Core"
]
]
"text_match" => 610246614239412226
"text_match_info" => array:7 [
"best_field_score" => "1108091338752"
"best_field_weight" => 15
"fields_matched" => 2
"num_tokens_dropped" => 0
"score" => "610246614239412226"
"tokens_matched" => 1
"typo_prefix_score" => 0
]
]
1 => array:5 [
"document" => array:48 [
"asic.foundry" => []
"asic.foundry_node" => []
"asic.foundry_node_process" => []
"asic.node" => []
"asic.node_foundry" => []
"blockdiagram" => "/upload/catalog/product/blockdiagram/15584/icon_32-bit-embedded-risc-v-processor-core-66bb8019afc14.png.webp"
"category.id" => array:1 [
0 => 643
]
"category.name" => array:1 [
0 => "RISC-V Processor IP"
]
"category.slug" => []
"created_at" => 1645714442
"id" => "15584"
"keyfeatures" => """
<ul>\r\n
\t<li>32-bit RISC-V core</li>\r\n
\t<li>Available in two versions:\r\n
\t<ul>\r\n
\t\t<li>RV32IMC</li>\r\n
\t\t<li>RV32IMCF</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>32 general purpose registers</li>\r\n
\t<li>Either parallel multiplier</li>\r\n
\t<li>3-stage pipeline</li>\r\n
\t<li>Dynamic branch predictor</li>\r\n
\t<li>RISC-V privilege mode support:\r\n
\t<ul>\r\n
\t\t<li>Machine, User</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Internal interrupt controller\r\n
\t<ul>\r\n
\t\t<li>Up to 256 sources</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Optional FPU (L30F)</li>\r\n
\t<li>Optional instruction and data tightly coupled memories (TCM)</li>\r\n
\t<li>Optional 8 or 16 PMP regions</li>\r\n
\t<li>Optional L1 data and instruction caches</li>\r\n
\t<li>Standard RISC-V CLINT\r\n
\t<ul>\r\n
\t\t<li>Up to 256 sources</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Wakeup interrupt controller</li>\r\n
\t<li>NMI</li>\r\n
\t<li>On-chip debugger\r\n
\t<ul>\r\n
\t\t<li>RISC-V Debug module</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>2/4 pin JTAG</li>\r\n
\t<li>2-8 breakpoints/watchpoints</li>\r\n
</ul>
"""
"keyfeatures_cn" => ""
"keywords" => "Processor, RISC-V, RISCV, Microcontroller"
"logo" => "codasip23-66bb478fde085.webp"
"logo2" => "codasip23-66bb478fde085.webp"
"name" => "asic.node"
"overview" => """
<p>The L31(F) is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requirements. The core has a 3-stage pipeline and has 32 general-purpose registers.<br />\r\n
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.<br />\r\n
Like with all Codasip RISC-V cores, it is possible to create custom instructions using Codasip Studio to extend the L31 and to generate corresponding hardware and software development kits.<br />\r\n
<br />\r\n
</p>
"""
"overview_cn" => ""
"partnumber" => "Codasip L31(F)"
"priority" => 91
"priority_taxo" => 1
"productTypes" => array:1 [
0 => "sip"
]
"provider.id" => 294
"provider.name" => "Codasip"
"provider.object" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"provider.priority" => 571
"provider.slug" => "codasip"
"published_as_new_at" => 0
"seofeatures" => """
<ul>\r\n
\t<li>32 bit,</li>\r\n
\t<li>3-stage pipeline,</li>\r\n
\t<li>32 registers</li>\r\n
</ul>
"""
"seofeatures_cn" => ""
"shortdescription" => "32 Bit - Embedded RISC-V Processor Core"
"shortdescription_cn" => ""
"slug" => "32-bit-embedded-risc-v-processor-core"
"sortable_id" => 15584
"taxo0" => array:1 [
0 => 1
]
"taxo1" => array:1 [
0 => 9
]
"taxo2" => array:1 [
0 => 99
]
"taxo3" => array:1 [
0 => 643
]
"taxo4" => []
"taxo5" => []
"taxo6" => []
"taxo7" => []
"taxo8" => []
"text_high_priority" => "Codasip L31(F) 32 Bit - Embedded RISC-V Processor Core"
"text_low_priority" => """
The L31(F) is a small efficient 32-bit embedded RISC-V processor aimed at systems with more modest processing requirements. core has 3-stage pipeline and 32 general-purpose registers.\r\n
The includes optional L1 data instruction caches TCM 8 or 16 PMP regions an interrupt controller Debug module optionally PC trace.\r\n
Like all Codasip cores it possible to create custom instructions using Studio extend the L31 generate corresponding hardware software development kits.\r\n
\r\n
\r\n
\t32-bit core\r\n
\tAvailable in two versions:\r\n
\t\r\n
\t\tRV32IMC\r\n
\t\tRV32IMCF\r\n
\t\r\n
\t\r\n
\t32 general purpose registers\r\n
\tEither parallel multiplier\r\n
\t3-stage pipeline\r\n
\tDynamic branch predictor\r\n
\tRISC-V privilege mode support:\r\n
\t\r\n
\t\tMachine User\r\n
\t\r\n
\t\r\n
\tInternal controller\r\n
\t\r\n
\t\tUp 256 sources\r\n
\t\r\n
\t\r\n
\tOptional FPU (L30F)\r\n
\tOptional tightly coupled memories (TCM)\r\n
\tOptional regions\r\n
\tOptional caches\r\n
\tStandard CLINT\r\n
\t\r\n
\t\tUp sources\r\n
\t\r\n
\t\r\n
\tWakeup controller\r\n
\tNMI\r\n
\tOn-chip debugger\r\n
\t\r\n
\t\tRISC-V module\r\n
\t\r\n
\t\r\n
\t2/4 pin JTAG\r\n
\t2-8 breakpoints/watchpoints\r\n
"""
"text_medium_priority" => "Processor RISC-V RISCV Microcontroller"
"updated_at" => 1724273456
]
"highlight" => array:2 [
"text_high_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> L31(F) 32 Bit - Embedded RISC-V Processor Core"
]
"text_low_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\r\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"highlights" => array:2 [
0 => array:3 [
"field" => "text_high_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> L31(F) 32 Bit - Embedded RISC-V Processor Core"
]
1 => array:3 [
"field" => "text_low_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\r\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"text_match" => 610246614239412226
"text_match_info" => array:7 [
"best_field_score" => "1108091338752"
"best_field_weight" => 15
"fields_matched" => 2
"num_tokens_dropped" => 0
"score" => "610246614239412226"
"tokens_matched" => 1
"typo_prefix_score" => 0
]
]
2 => array:5 [
"document" => array:48 [
"asic.foundry" => []
"asic.foundry_node" => []
"asic.foundry_node_process" => []
"asic.node" => []
"asic.node_foundry" => []
"blockdiagram" => "/upload/catalog/product/blockdiagram/15583/icon_32-bit-compact-risc-v-processor-core-66bb80167f6eb.png.webp"
"category.id" => array:1 [
0 => 643
]
"category.name" => array:1 [
0 => "RISC-V Processor IP"
]
"category.slug" => []
"created_at" => 1645714199
"id" => "15583"
"keyfeatures" => """
<ul>\r\n
\t<li>32-bit RISC-V core</li>\r\n
\t<li>RV32EMC instruction set</li>\r\n
\t<li>16 general purpose registers</li>\r\n
\t<li>Either small sequential multiplier</li>\r\n
\t<li>3-stage pipeline</li>\r\n
\t<li>RISC-V privilege mode support:\r\n
\t<ul>\r\n
\t\t<li>Machine</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Standard RISC-V CLINT\r\n
\t<ul>\r\n
\t\t<li>Up to 256 sources</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Wakeup interrupt controller</li>\r\n
\t<li>NMI</li>\r\n
\t<li>On-chip debugger\r\n
\t<ul>\r\n
\t\t<li>RISC-V Debug module</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>2/4 pin JTAG</li>\r\n
\t<li>2-8 breakpoints/watchpoints</li>\r\n
</ul>
"""
"keyfeatures_cn" => ""
"keywords" => "Processor, RISC-V, RISCV, Microcontroller"
"logo" => "codasip23-66bb478fde085.webp"
"logo2" => "codasip23-66bb478fde085.webp"
"name" => "asic.node"
"overview" => """
<p>The L11 is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requirements. The core has a 3-stage pipeline and with 16 general purpose registers.<br />\r\n
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.<br />\r\n
Like with all Codasip RISC-V cores, it is possible to create custom instructions using Codasip Studio to extend the L10 and to generate corresponding hardware and software development kits.<br />\r\n
</p>
"""
"overview_cn" => ""
"partnumber" => "Codasip L11"
"priority" => 91
"priority_taxo" => 1
"productTypes" => array:1 [
0 => "sip"
]
"provider.id" => 294
"provider.name" => "Codasip"
"provider.object" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"provider.priority" => 571
"provider.slug" => "codasip"
"published_as_new_at" => 0
"seofeatures" => """
<ul>\r\n
\t<li>32-bit RISC-V core</li>\r\n
\t<li>RV32EMC instruction set</li>\r\n
\t<li>16 general purpose registers</li>\r\n
</ul>
"""
"seofeatures_cn" => ""
"shortdescription" => "32 bit - Compact RISC-V Processor Core"
"shortdescription_cn" => ""
"slug" => "32-bit-compact-risc-v-processor-core"
"sortable_id" => 15583
"taxo0" => array:1 [
0 => 1
]
"taxo1" => array:1 [
0 => 9
]
"taxo2" => array:1 [
0 => 99
]
"taxo3" => array:1 [
0 => 643
]
"taxo4" => []
"taxo5" => []
"taxo6" => []
"taxo7" => []
"taxo8" => []
"text_high_priority" => "Codasip L11 32 bit - Compact RISC-V Processor Core"
"text_low_priority" => """
The L11 is a small efficient 32-bit embedded RISC-V processor aimed at systems with more modest processing requirements. core has 3-stage pipeline and 16 general purpose registers.\r\n
The includes optional L1 data instruction caches TCM 8 or PMP regions an interrupt controller Debug module optionally PC trace.\r\n
Like all Codasip cores it possible to create custom instructions using Studio extend the L10 generate corresponding hardware software development kits.\r\n
\r\n
\t32-bit core\r\n
\tRV32EMC set\r\n
\t16 registers\r\n
\tEither sequential multiplier\r\n
\t3-stage pipeline\r\n
\tRISC-V privilege mode support:\r\n
\t\r\n
\t\tMachine\r\n
\t\r\n
\t\r\n
\tStandard CLINT\r\n
\t\r\n
\t\tUp 256 sources\r\n
\t\r\n
\t\r\n
\tWakeup controller\r\n
\tNMI\r\n
\tOn-chip debugger\r\n
\t\r\n
\t\tRISC-V module\r\n
\t\r\n
\t\r\n
\t2/4 pin JTAG\r\n
\t2-8 breakpoints/watchpoints\r\n
"""
"text_medium_priority" => "Processor RISC-V RISCV Microcontroller"
"updated_at" => 1724329853
]
"highlight" => array:2 [
"text_high_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> L11 32 bit - Compact RISC-V Processor Core"
]
"text_low_priority" => array:2 [
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\r\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"highlights" => array:2 [
0 => array:3 [
"field" => "text_high_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => "<mark>Codasip</mark> L11 32 bit - Compact RISC-V Processor Core"
]
1 => array:3 [
"field" => "text_low_priority"
"matched_tokens" => array:1 [ …1]
"snippet" => """
PC trace.\r\n
Like all <mark>Codasip</mark> cores it possible to
"""
]
]
"text_match" => 610246614239412226
"text_match_info" => array:7 [
"best_field_score" => "1108091338752"
"best_field_weight" => 15
"fields_matched" => 2
"num_tokens_dropped" => 0
"score" => "610246614239412226"
"tokens_matched" => 1
"typo_prefix_score" => 0
]
]
3 => array:5 [
"document" => array:48 [
"asic.foundry" => []
"asic.foundry_node" => []
"asic.foundry_node_process" => []
"asic.node" => []
"asic.node_foundry" => []
"blockdiagram" => "/upload/catalog/product/blockdiagram/14641/icon_compact-risc-v-processor-32-bit-3-stage-pipeline-32-registers-66bb791106370.png.webp"
"category.id" => array:1 [
0 => 643
]
"category.name" => array:1 [
0 => "RISC-V Processor IP"
]
"category.slug" => []
"created_at" => 1614788957
"id" => "14641"
"keyfeatures" => """
<ul>\r\n
\t<li>32-bit RISC-V core</li>\r\n
\t<li>Available in two versions:\r\n
\t<ul>\r\n
\t\t<li>RV32IMC</li>\r\n
\t\t<li>RV32IMCF</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>32 general purpose registers</li>\r\n
\t<li>Either parallel multiplier</li>\r\n
\t<li>3-stage pipeline</li>\r\n
\t<li>Dynamic branch predictor</li>\r\n
\t<li>RISC-V privilege mode support:\r\n
\t<ul>\r\n
\t\t<li>Machine, User</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Internal interrupt controller\r\n
\t<ul>\r\n
\t\t<li>Up to 256 sources</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Optional FPU (L30F)</li>\r\n
\t<li>Optional instruction and data tightly coupled memories (TCM)</li>\r\n
\t<li>Optional 8 or 16 PMP regions</li>\r\n
\t<li>Optional L1 data and instruction caches</li>\r\n
\t<li>Standard RISC-V CLINT\r\n
\t<ul>\r\n
\t\t<li>Up to 256 sources</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Wakeup interrupt controller</li>\r\n
\t<li>NMI</li>\r\n
\t<li>On-chip debugger\r\n
\t<ul>\r\n
\t\t<li>RISC-V Debug module</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>2/4 pin JTAG</li>\r\n
\t<li>2-8 breakpoints/watchpoints</li>\r\n
</ul>
"""
"keyfeatures_cn" => ""
"keywords" => "Processor, RISC-V, RISCV, Microcontroller"
"logo" => "codasip23-66bb478fde085.webp"
"logo2" => "codasip23-66bb478fde085.webp"
"name" => "asic.node"
"overview" => """
<p>The L30(F) is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requirements. The core has a 3-stage pipeline and has 32 general-purpose registers.<br />\r\n
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.<br />\r\n
Like with all Codasip RISC-V cores, it is possible to create custom instructions using Codasip Studio to extend the L30 and to generate corresponding hardware and software development kits.<br />\r\n
</p>
"""
"overview_cn" => ""
"partnumber" => "Codasip L30(F)"
"priority" => 1
"priority_taxo" => 1
"productTypes" => array:1 [
0 => "sip"
]
"provider.id" => 294
"provider.name" => "Codasip"
"provider.object" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"provider.priority" => 571
"provider.slug" => "codasip"
"published_as_new_at" => 0
"seofeatures" => """
<ul>\r\n
\t<li>32-bit RISC-V core</li>\r\n
\t<li>Available in two versions:</li>\r\n
\t<li>32 general purpose registers</li>\r\n
\t<li>Either parallel multiplier</li>\r\n
</ul>
"""
"seofeatures_cn" => ""
"shortdescription" => "Compact RISC-V Processor - 32 bit, 3-stage pipeline, 32 registers"
"shortdescription_cn" => ""
"slug" => "compact-risc-v-processor-32-bit-3-stage-pipeline-32-registers"
"sortable_id" => 14641
"taxo0" => array:1 [
0 => 1
]
"taxo1" => array:1 [ …1]
"taxo2" => array:1 [ …1]
"taxo3" => array:1 [ …1]
"taxo4" => []
"taxo5" => []
"taxo6" => []
"taxo7" => []
"taxo8" => []
"text_high_priority" => "Codasip L30(F) Compact RISC-V Processor - 32 bit 3-stage pipeline registers"
"text_low_priority" => """
The L30(F) is a small efficient 32-bit embedded RISC-V processor aimed at systems with more modest processing requirements. core has 3-stage pipeline and 32 general-purpose registers.\r\n
The includes optional L1 data instruction caches TCM 8 or 16 PMP regions an interrupt controller Debug module optionally PC trace.\r\n
Like all Codasip cores it possible to create custom instructions using Studio extend the L30 generate corresponding hardware software development kits.\r\n
\r\n
\t32-bit core\r\n
\tAvailable in two versions:\r\n
\t\r\n
\t\tRV32IMC\r\n
\t\tRV32IMCF\r\n
\t\r\n
\t\r\n
\t32 general purpose registers\r\n
\tEither parallel multiplier\r\n
\t3-stage pipeline\r\n
\tDynamic branch predictor\r\n
\tRISC-V privilege mode support:\r\n
\t\r\n
\t\tMachine User\r\n
\t\r\n
\t\r\n
\tInternal controller\r\n
\t\r\n
\t\tUp 256 sources\r\n
\t\r\n
\t\r\n
\tOptional FPU (L30F)\r\n
\tOptional tightly coupled memories (TCM)\r\n
\tOptional regions\r\n
\tOptional caches\r\n
\tStandard CLINT\r\n
\t\r\n
\t\tUp sources\r\n
\t\r\n
\t\r\n
\tWakeup controller\r\n
\tNMI\r\n
\tOn-chip debugger\r\n
\t\r\n
\t\tRISC-V module\r\n
\t\r\n
\t\r\n
\t2/4 pin JTAG\r\n
\t2-8 breakpoints/watchpoints\r\n
"""
"text_medium_priority" => "Processor RISC-V RISCV Microcontroller"
"updated_at" => 1724274361
]
"highlight" => array:2 [
"text_high_priority" => array:2 [ …2]
"text_low_priority" => array:2 [ …2]
]
"highlights" => array:2 [
0 => array:3 [ …3]
1 => array:3 [ …3]
]
"text_match" => 610246614239412226
"text_match_info" => array:7 [
"best_field_score" => "1108091338752"
"best_field_weight" => 15
"fields_matched" => 2
"num_tokens_dropped" => 0
"score" => "610246614239412226"
"tokens_matched" => 1
"typo_prefix_score" => 0
]
]
4 => array:5 [
"document" => array:48 [
"asic.foundry" => []
"asic.foundry_node" => []
"asic.foundry_node_process" => []
"asic.node" => []
"asic.node_foundry" => []
"blockdiagram" => "/upload/catalog/product/blockdiagram/14236/icon_64-bit-risc-v-application-processor-core-66bb760b9ef28.png.webp"
"category.id" => array:1 [ …1]
"category.name" => array:1 [ …1]
"category.slug" => []
"created_at" => 1607105972
"id" => "14236"
"keyfeatures" => "<ul><li>64-bit RISC-V core</li><ul><li> RV64GC (GC=IMAFDC)</li></ul><li>Linux capable</li><li>In-order 7-stage pipeline</li><li>RISC-V mode support:</li><ul><li> Machine</li><li> Supervisor</li><li> User</li></ul><li>Internal interrupt controller</li><ul><li> Up to 256 sources</li></ul><li>Dynamic jump prediction</li><li>Optional FPU</li><li>Integrated L1 data and instruction caches</li><li>L2 cache coherence for up to 4 cores</li><li>MMU</li><li>On-chip debugger</li><ul><li> JTAG and RISC-V Debug module</li></ul><li>>1GHz clock in 22 nm</li></ul>"
"keyfeatures_cn" => ""
"keywords" => "RISC-V,RISCV,64-bit,Linux"
"logo" => "codasip23-66bb478fde085.webp"
"logo2" => "codasip23-66bb478fde085.webp"
"name" => "asic.node"
"overview" => """
The A70 is a powerful 64-bit RISC-V application processor aimed at systems running Linux. The core has an in-order 7-stage pipeline enabling greater than 1 GHz frequencies in 22nm HPC. <br />\n
The core includes integrated L1 data and instruction caches, an interrupt controller and RISC-V Debug module optionally with PC trace.<br />\n
Like all Codasip RISC-V cores it is possible to create custom instructions using Codasip Studio to extend the ISA and to generate corresponding hardware and software development kits.<br />\n
"""
"overview_cn" => ""
"partnumber" => "Codasip A70-MP"
"priority" => 41
"priority_taxo" => 1
"productTypes" => array:1 [ …1]
"provider.id" => 294
"provider.name" => "Codasip"
"provider.object" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"provider.priority" => 571
"provider.slug" => "codasip"
"published_as_new_at" => 0
"seofeatures" => "<ul><li>High computational throughput with 7-stage pipeline and branch predictor</li><li>Support for RISC-V single and double precision FPU</li></ul>"
"seofeatures_cn" => ""
"shortdescription" => "64-bit RISC-V Application Processor Core"
"shortdescription_cn" => ""
"slug" => "64-bit-risc-v-application-processor-core-1"
"sortable_id" => 14236
"taxo0" => array:1 [ …1]
"taxo1" => array:1 [ …1]
"taxo2" => array:1 [ …1]
"taxo3" => array:1 [ …1]
"taxo4" => []
"taxo5" => []
"taxo6" => []
"taxo7" => []
"taxo8" => []
"text_high_priority" => "Codasip A70-MP 64-bit RISC-V Application Processor Core"
"text_low_priority" => """
The A70 is a powerful 64-bit RISC-V application processor aimed at systems running Linux. core has an in-order 7-stage pipeline enabling greater than 1 GHz frequencies in 22nm HPC. \n
The includes integrated L1 data and instruction caches interrupt controller Debug module optionally with PC trace.\n
Like all Codasip cores it possible to create custom instructions using Studio extend the ISA generate corresponding hardware software development kits.\n
RV64GC (GC=IMAFDC)Linux capableIn-order pipelineRISC-V mode support: Machine Supervisor UserInternal Up 256 sourcesDynamic jump predictionOptional FPUIntegrated cachesL2 cache coherence for up 4 coresMMUOn-chip debugger JTAG module>1GHz clock 22 nm
"""
"text_medium_priority" => "RISC-V RISCV 64-bit Linux "
"updated_at" => 1695309751
]
"highlight" => array:2 [
"text_high_priority" => array:2 [ …2]
"text_low_priority" => array:2 [ …2]
]
"highlights" => array:2 [
0 => array:3 [ …3]
1 => array:3 [ …3]
]
"text_match" => 610246614239412226
"text_match_info" => array:7 [
"best_field_score" => "1108091338752"
"best_field_weight" => 15
"fields_matched" => 2
"num_tokens_dropped" => 0
"score" => "610246614239412226"
"tokens_matched" => 1
"typo_prefix_score" => 0
]
]
5 => array:5 [
"document" => array:48 [
"asic.foundry" => []
"asic.foundry_node" => []
"asic.foundry_node_process" => []
"asic.node" => []
"asic.node_foundry" => []
"blockdiagram" => "/upload/catalog/product/blockdiagram/14235/icon_64-bit-risc-v-application-processor-core-66bb76083e20a.png.webp"
"category.id" => array:1 [ …1]
"category.name" => array:1 [ …1]
"category.slug" => []
"created_at" => 1607105564
"id" => "14235"
"keyfeatures" => "<ul><li>64-bit RISC-V core</li><ul><li> RV64GC (GC=IMAFDC)</li></ul><li>Linux capable</li><li>In-order 7-stage pipeline</li><li>RISC-V mode support:</li><ul><li> Machine</li><li> Supervisor</li><li> User</li></ul><li>Internal interrupt controller</li><ul><li> Up to 256 sources</li></ul><li>Dynamic jump prediction</li><li>Optional FPU</li><li>Integrated L1 data and instruction caches</li><li>MMU</li><li>On-chip debugger</li><ul><li> JTAG and RISC-V Debug module</li></ul><li>>1GHz clock in 22 nm</li></ul>"
"keyfeatures_cn" => ""
"keywords" => "RISC-V,RISCV,64-bit,Linux"
"logo" => "codasip23-66bb478fde085.webp"
"logo2" => "codasip23-66bb478fde085.webp"
"name" => "asic.node"
"overview" => """
The A70 is a powerful 64-bit RISC-V application processor aimed at systems running Linux. The core has an in-order 7-stage pipeline enabling greater than 1 GHz frequencies in 22nm HPC. <br />\n
The core includes integrated L1 data and instruction caches, an interrupt controller and RISC-V Debug module optionally with PC trace.<br />\n
Like all Codasip RISC-V cores it is possible to create custom instructions using Codasip Studio to extend the ISA and to generate corresponding hardware and software development kits.<br />\n
Tensor Flow Lite Micro is supported<br />\n
"""
"overview_cn" => ""
"partnumber" => "Codasip A70"
"priority" => 101
"priority_taxo" => 1
"productTypes" => array:1 [ …1]
"provider.id" => 294
"provider.name" => "Codasip"
"provider.object" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"provider.priority" => 571
"provider.slug" => "codasip"
"published_as_new_at" => 0
"seofeatures" => "<ul><li>64-bit RISC-V core</li><li>Linux capable</li><li>In-order 7-stage pipeline</li></ul>"
"seofeatures_cn" => ""
"shortdescription" => "64-bit RISC-V Application Processor Core"
"shortdescription_cn" => ""
"slug" => "64-bit-risc-v-application-processor-core"
"sortable_id" => 14235
"taxo0" => array:1 [ …1]
"taxo1" => array:1 [ …1]
"taxo2" => array:1 [ …1]
"taxo3" => array:1 [ …1]
"taxo4" => []
"taxo5" => []
"taxo6" => []
"taxo7" => []
"taxo8" => []
"text_high_priority" => "Codasip A70 64-bit RISC-V Application Processor Core"
"text_low_priority" => """
The A70 is a powerful 64-bit RISC-V application processor aimed at systems running Linux. core has an in-order 7-stage pipeline enabling greater than 1 GHz frequencies in 22nm HPC. \n
The includes integrated L1 data and instruction caches interrupt controller Debug module optionally with PC trace.\n
Like all Codasip cores it possible to create custom instructions using Studio extend the ISA generate corresponding hardware software development kits.\n
Tensor Flow Lite Micro supported\n
RV64GC (GC=IMAFDC)Linux capableIn-order pipelineRISC-V mode support: Machine Supervisor UserInternal Up 256 sourcesDynamic jump predictionOptional FPUIntegrated cachesMMUOn-chip debugger JTAG module>1GHz clock 22 nm
"""
"text_medium_priority" => "RISC-V RISCV 64-bit Linux "
"updated_at" => 1695309729
]
"highlight" => array:2 [
"text_high_priority" => array:2 [ …2]
"text_low_priority" => array:2 [ …2]
]
"highlights" => array:2 [
0 => array:3 [ …3]
1 => array:3 [ …3]
]
"text_match" => 610246614239412226
"text_match_info" => array:7 [
"best_field_score" => "1108091338752"
"best_field_weight" => 15
"fields_matched" => 2
"num_tokens_dropped" => 0
"score" => "610246614239412226"
"tokens_matched" => 1
"typo_prefix_score" => 0
]
]
6 => array:5 [
"document" => array:48 [
"asic.foundry" => []
"asic.foundry_node" => []
"asic.foundry_node_process" => []
"asic.node" => []
"asic.node_foundry" => []
"blockdiagram" => "/upload/catalog/product/blockdiagram/13700/icon_processor-development-toolset-66bb724ab758f.png.webp"
"category.id" => array:1 [ …1]
"category.name" => array:1 [ …1]
"category.slug" => []
"created_at" => 1585330653
"id" => "13700"
"keyfeatures" => """
<ul>\r\n
\t<li>A unified development model describing the processor in a single CodAL description</li>\r\n
\t<li>High performance processor synthesis</li>\r\n
\t<li>Complete UVM verification environment</li>\r\n
\t<li>Advanced profiling and analysis</li>\r\n
\t<li>Compatible with Codasip RISC-V cores</li>\r\n
</ul>
"""
"keyfeatures_cn" => ""
"keywords" => "Processor, toolset, EDA, RISC-V, RISCV, ISS, SDK, HDK, UVM, CodAL, co-simulation,ASIP,domain-specific design"
"logo" => "codasip23-66bb478fde085.webp"
"logo2" => "codasip23-66bb478fde085.webp"
"name" => "asic.node"
"overview" => """
<p>Codasip Studio is a complete set of Electronic Design Automation (EDA) tools for processor design and customization. The level of automation is unmatched on the market, and produces fast and efficient results.<br />\r\n
<br />\r\n
Our approach at Codasip is to automate the development of processor cores by using a high-level description in the CodAL processor description language and generating the design implementation, verification environment, virtual system prototype, and a complete software toolchain using Codasip Studio.<br />\r\n
<br />\r\n
In addition to its design capabilities, Codasip Studio includes powerful multiprocessor programming, debugging and profiling features, enabling the development of complex processor designs with ease.<br />\r\n
<br />\r\n
Codasip Studio is built upon open standards and software including Eclipse, LLVM, Verilog, SystemVerilog, and UVM.</p>
"""
"overview_cn" => ""
"partnumber" => "Codasip Studio"
"priority" => 91
"priority_taxo" => 1
"productTypes" => array:1 [ …1]
"provider.id" => 294
"provider.name" => "Codasip"
"provider.object" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"provider.priority" => 571
"provider.slug" => "codasip"
"published_as_new_at" => 0
"seofeatures" => """
<ul>\r\n
\t<li>A unified development model describing the processor in a single CodAL description</li>\r\n
\t<li>High performance processor synthesis</li>\r\n
\t<li>Complete UVM verification environment</li>\r\n
\t<li>Advanced profiling and analysis</li>\r\n
</ul>
"""
"seofeatures_cn" => ""
"shortdescription" => "Processor Development Toolset"
"shortdescription_cn" => ""
"slug" => "processor-development-toolset"
"sortable_id" => 13700
"taxo0" => array:1 [ …1]
"taxo1" => array:1 [ …1]
"taxo2" => array:1 [ …1]
"taxo3" => array:1 [ …1]
"taxo4" => []
"taxo5" => []
"taxo6" => []
"taxo7" => []
"taxo8" => []
"text_high_priority" => "Codasip Studio Processor Development Toolset"
"text_low_priority" => """
Codasip Studio is a complete set of Electronic Design Automation (EDA) tools for processor design and customization. The level automation unmatched on the market produces fast efficient results.\r\n
\r\n
Our approach at to automate development cores by using high-level description in CodAL language generating implementation verification environment virtual system prototype software toolchain Studio.\r\n
\r\n
In addition its capabilities includes powerful multiprocessor programming debugging profiling features enabling complex designs with ease.\r\n
\r\n
Codasip built upon open standards including Eclipse LLVM Verilog SystemVerilog UVM. \r\n
\tA unified model describing single description\r\n
\tHigh performance synthesis\r\n
\tComplete UVM environment\r\n
\tAdvanced analysis\r\n
\tCompatible RISC-V cores\r\n
"""
"text_medium_priority" => "Processor toolset EDA RISC-V RISCV ISS SDK HDK UVM CodAL co-simulation ASIP domain-specific design"
"updated_at" => 1724273514
]
"highlight" => array:2 [
"text_high_priority" => array:2 [ …2]
"text_low_priority" => array:2 [ …2]
]
"highlights" => array:2 [
0 => array:3 [ …3]
1 => array:3 [ …3]
]
"text_match" => 610246614239412226
"text_match_info" => array:7 [
"best_field_score" => "1108091338752"
"best_field_weight" => 15
"fields_matched" => 2
"num_tokens_dropped" => 0
"score" => "610246614239412226"
"tokens_matched" => 1
"typo_prefix_score" => 0
]
]
7 => array:5 [
"document" => array:48 [
"asic.foundry" => []
"asic.foundry_node" => []
"asic.foundry_node_process" => []
"asic.node" => []
"asic.node_foundry" => []
"blockdiagram" => "/upload/catalog/product/blockdiagram/11810/icon_compact-efficient-64-bit-risc-v-processor-with-5-stage-pipeline-66bb6723b03a8.png.webp"
"category.id" => array:1 [ …1]
"category.name" => array:1 [ …1]
"category.slug" => []
"created_at" => 1511859747
"id" => "11810"
"keyfeatures" => "<ul><li>64-bit RISC-V core</li><ul><li> H50X supports RV64IMC</li><li> H50XF supports RV64IMCF</li></ul><li>Fully parallel multiplier</li><li>5-stage pipeline</li><li>Dynamic Branch Predictor</li><li>RISC-V mode support:</li><ul><li> Machine, User</li></ul><li>Internal interrupt controller</li><ul><li> Up to 256 sources</li></ul><li>FPU (H50F)</li><li>Optional instruction and data tightly coupled memories (TCM)</li><li>Optional 8 or 16 PMP regions</li><li>Optional L1 data and instruction caches</li><li>On-chip debugger</li><ul><li> JTAG and RISC-V Debug module</li></ul></ul>"
"keyfeatures_cn" => ""
"keywords" => "RISC-V, RISCV, Processor"
"logo" => "codasip23-66bb478fde085.webp"
"logo2" => "codasip23-66bb478fde085.webp"
"name" => "asic.node"
"overview" => """
The H50 is an entry level, compact, efficient 64-bit embedded RISC-V processor aimed at embedded systems requiring a large address space. The core has a 5-stage pipeline and is offered in two versions. <br />\n
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.<br />\n
Like with all Codasip RISC-V cores, it is possible to create custom instructions using Codasip Studio to extend the H50 and to generate corresponding hardware and software development kits.<br />\n
"""
"overview_cn" => ""
"partnumber" => "Codasip H50(F)"
"priority" => 1
"priority_taxo" => 1
"productTypes" => array:1 [ …1]
"provider.id" => 294
"provider.name" => "Codasip"
"provider.object" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"provider.priority" => 571
"provider.slug" => "codasip"
"published_as_new_at" => 0
"seofeatures" => "<ul><li>Support for RV32IM</li><li>5-stage pipeline</li><li>Thirty-two 64-bit general purpose registers</li></ul>"
"seofeatures_cn" => ""
"shortdescription" => "Compact, efficient 64-bit RISC-V processor with 5-stage pipeline"
"shortdescription_cn" => ""
"slug" => "compact-efficient-64-bit-risc-v-processor-with-5-stage-pipeline"
"sortable_id" => 11810
"taxo0" => array:1 [ …1]
"taxo1" => array:1 [ …1]
"taxo2" => array:1 [ …1]
"taxo3" => array:1 [ …1]
"taxo4" => []
"taxo5" => []
"taxo6" => []
"taxo7" => []
"taxo8" => []
"text_high_priority" => "Codasip H50(F) Compact efficient 64-bit RISC-V processor with 5-stage pipeline"
"text_low_priority" => """
The H50 is an entry level compact efficient 64-bit embedded RISC-V processor aimed at systems requiring a large address space. core has 5-stage pipeline and offered in two versions. \n
The includes optional L1 data instruction caches TCM 8 or 16 PMP regions interrupt controller Debug module optionally with PC trace.\n
Like all Codasip cores it possible to create custom instructions using Studio extend the generate corresponding hardware software development kits.\n
H50X supports RV64IMC H50XF RV64IMCFFully parallel multiplier5-stage pipelineDynamic Branch PredictorRISC-V mode support: Machine UserInternal Up 256 sourcesFPU (H50F)Optional tightly coupled memories (TCM)Optional regionsOptional cachesOn-chip debugger JTAG
"""
"text_medium_priority" => "RISC-V RISCV Processor"
"updated_at" => 1694450608
]
"highlight" => array:2 [
"text_high_priority" => array:2 [ …2]
"text_low_priority" => array:2 [ …2]
]
"highlights" => array:2 [
0 => array:3 [ …3]
1 => array:3 [ …3]
]
"text_match" => 610246614239412226
"text_match_info" => array:7 [
"best_field_score" => "1108091338752"
"best_field_weight" => 15
"fields_matched" => 2
"num_tokens_dropped" => 0
"score" => "610246614239412226"
"tokens_matched" => 1
"typo_prefix_score" => 0
]
]
8 => array:5 [
"document" => array:48 [
"asic.foundry" => []
"asic.foundry_node" => []
"asic.foundry_node_process" => []
"asic.node" => []
"asic.node_foundry" => []
"blockdiagram" => "/upload/catalog/product/blockdiagram/9729/icon_risc-v-processor-32-bit-5-stage-pipeline-66bb5e01b1d4d.png.webp"
"category.id" => array:1 [ …1]
"category.name" => array:1 [ …1]
"category.slug" => []
"created_at" => 1477431465
"id" => "9729"
"keyfeatures" => """
<ul>\r\n
\t<li>32-bit RISC-V core\r\n
\t<ul>\r\n
\t\t<li>The L50 supports the RV32IMC ISA</li>\r\n
\t\t<li>The L50F supports the RV32IMCF ISA</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Fully parallel multiplier</li>\r\n
\t<li>5-stage pipeline</li>\r\n
\t<li>Dynamic Branch Predictor</li>\r\n
\t<li>RISC-V privilege mode support:\r\n
\t<ul>\r\n
\t\t<li>Machine, User</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Internal interrupt controller\r\n
\t<ul>\r\n
\t\t<li>Up to 256 sources</li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Optional FPU (L50F)</li>\r\n
\t<li>Optional instruction and data tightly coupled memories (TCM)</li>\r\n
\t<li>Optional 8 or 16 PMP regions</li>\r\n
\t<li>Optional L1 data and instruction caches</li>\r\n
\t<li>On-chip debugger\r\n
\t<ul>\r\n
\t\t<li>JTAG and RISC-V Debug module</li>\r\n
\t</ul>\r\n
\t</li>\r\n
</ul>
"""
"keyfeatures_cn" => ""
"keywords" => "RISC-V, RISCV, Processor"
"logo" => "codasip23-66bb478fde085.webp"
"logo2" => "codasip23-66bb478fde085.webp"
"name" => "asic.node"
"overview" => """
<p>The L50(F) is a medium-sized, efficient 32-bit embedded RISC-V processor aimed at embedded systems with mid-range processing requirements. The core has a 5-stage pipeline. The L50F has a floating point unit.<br />\r\n
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.<br />\r\n
Like with all Codasip RISC-V cores, it is possible to create custom instructions using Codasip Studio to extend the L50 or L50F and to generate corresponding hardware and software development kits.</p>
"""
"overview_cn" => ""
"partnumber" => "Codasip L50(F)"
"priority" => 1
"priority_taxo" => 1
"productTypes" => array:1 [ …1]
"provider.id" => 294
"provider.name" => "Codasip"
"provider.object" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"provider.priority" => 571
"provider.slug" => "codasip"
"published_as_new_at" => 0
"seofeatures" => """
<ul>\r\n
\t<li>Support for RV32IM/RV64IM</li>\r\n
\t<li>5-stage pipeline</li>\r\n
\t<li>32 or 64bit general purpose registers</li>\r\n
</ul>
"""
"seofeatures_cn" => ""
"shortdescription" => "RISC-V processor - 32 bit, 5-stage pipeline"
"shortdescription_cn" => ""
"slug" => "risc-v-processor-32-bit-5-stage-pipeline"
"sortable_id" => 9729
"taxo0" => array:1 [ …1]
"taxo1" => array:1 [ …1]
"taxo2" => array:1 [ …1]
"taxo3" => array:1 [ …1]
"taxo4" => []
"taxo5" => []
"taxo6" => []
"taxo7" => []
"taxo8" => []
"text_high_priority" => "Codasip L50(F) RISC-V processor - 32 bit 5-stage pipeline"
"text_low_priority" => """
The L50(F) is a medium-sized efficient 32-bit embedded RISC-V processor aimed at systems with mid-range processing requirements. core has 5-stage pipeline. L50F floating point unit.\r\n
The includes optional L1 data and instruction caches TCM 8 or 16 PMP regions an interrupt controller Debug module optionally PC trace.\r\n
Like all Codasip cores it possible to create custom instructions using Studio extend the L50 generate corresponding hardware software development kits. \r\n
\t32-bit core\r\n
\t\r\n
\t\tThe supports RV32IMC ISA\r\n
\t\tThe RV32IMCF ISA\r\n
\t\r\n
\t\r\n
\tFully parallel multiplier\r\n
\t5-stage pipeline\r\n
\tDynamic Branch Predictor\r\n
\tRISC-V privilege mode support:\r\n
\t\r\n
\t\tMachine User\r\n
\t\r\n
\t\r\n
\tInternal controller\r\n
\t\r\n
\t\tUp 256 sources\r\n
\t\r\n
\t\r\n
\tOptional FPU (L50F)\r\n
\tOptional tightly coupled memories (TCM)\r\n
\tOptional regions\r\n
\tOptional caches\r\n
\tOn-chip debugger\r\n
\t\r\n
\t\tJTAG module\r\n
\t\r\n
\t\r\n
"""
"text_medium_priority" => "RISC-V RISCV Processor"
"updated_at" => 1724273763
]
"highlight" => array:2 [
"text_high_priority" => array:2 [ …2]
"text_low_priority" => array:2 [ …2]
]
"highlights" => array:2 [
0 => array:3 [ …3]
1 => array:3 [ …3]
]
"text_match" => 610246614239412226
"text_match_info" => array:7 [
"best_field_score" => "1108091338752"
"best_field_weight" => 15
"fields_matched" => 2
"num_tokens_dropped" => 0
"score" => "610246614239412226"
"tokens_matched" => 1
"typo_prefix_score" => 0
]
]
9 => array:5 [
"document" => array:48 [
"asic.foundry" => []
"asic.foundry_node" => []
"asic.foundry_node_process" => []
"asic.node" => []
"asic.node_foundry" => []
"blockdiagram" => "/upload/catalog/product/blockdiagram/18735/icon_picture2-3-674b14421d6b0.png.webp"
"category.id" => array:1 [ …1]
"category.name" => array:1 [ …1]
"category.slug" => []
"created_at" => 1714399022
"id" => "18735"
"keyfeatures" => """
<ul>\r\n
\t<li>Flexible use cases\r\n
\t<ul>\r\n
\t\t<li>Safety Island as a protected enclave of the device providing freedom of interface for the independent execution of safety-related application code. </li>\r\n
\t\t<li>Controller, running the safety-related application code. </li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>Proven technology\r\n
\t<ul>\r\n
\t\t<li>Based on the L31 silicon-proven embedded processor </li>\r\n
\t\t<li>State-of-the-art verification scheme brings quality and reliability </li>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<li>State-of-the-art safety and security\r\n
\t<ul>\r\n
\t\t<li>Dual-core lockstep provides a robust and well trusted approach to building high-reliability systems and meeting the stringent safety requirements of critical applications </li>\r\n
\t\t<li>\u{200B}L31AS increases security against certain threat scenarios and can help meet requirements for security certification </li>\r\n
\t</ul>\r\n
\t</li>\r\n
</ul>
"""
"keyfeatures_cn" => ""
"keywords" => "Processor, RISC-V, RISCV, Microcontroller, TuV SuD ISO 26262"
"logo" => "codasip23-66bb478fde085.webp"
"logo2" => "codasip23-66bb478fde085.webp"
"name" => "asic.node"
"overview" => """
<p>The L31AS is a 32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification. Part of our safety and security offering, this embedded processor is ideal either as a Main Controller or a Safety Island in a Functional Safety System.<br />\r\n
<br />\r\n
It includes 2 instances of the L31 in a dual-core lockstep configuration along with Physical Memory Protection as a security feature.<br />\r\n
</p>\r\n
\r\n
<p>L31AS is an in-order, 3-stage, single-issue RISC-V core targeted for automotive and other functional safety applications. It is based on the RV32IMC ISA. It includes physical memory protection. </p>\r\n
\r\n
<p>L31AS features separate Data and Instruction AHB-Lite interfaces, block-level gating in single-core configuration and performance counters. It uses the standard RISC-V debug specification with 4 debug triggers and Debug Memory Interface (DMI) as an APB interface that can be used to interface with external debuggers. </p>\r\n
\r\n
<p><strong>Certified for Functional Safety</strong></p>\r\n
\r\n
<p>The L31AS core is certified by TÜV SÜD according to the requirements set forth in ISO26262 up to ASIL B. It is delivered with a safety pack including a safety manual and a safety case report. </p>\r\n
\r\n
<p><strong>Software development</strong></p>\r\n
\r\n
<p>Using standard AMBA AHB Interface, L31AS can easily be connected to existing systems and interconnects.\u{202F}What is more, L31AS is designed to simplify software development, with essential features to support developers:\u{202F} </p>\r\n
\r\n
<ul>\r\n
\t<li><strong>Debug interface</strong>\u{202F}– using standard RISC-V Debug specification\u{202F}\u{202F} </li>\r\n
\t<li><strong>Instruction-accurate model</strong>\u{202F}–\u{202F}for fast execution of software, before hardware is available\u{202F} </li>\r\n
\t<li><strong>Cycle-accurate model</strong>\u{202F}–\u{202F}for software algorithm optimization, when time constraints require precise execution\u{202F} </li>\r\n
\t<li><strong>Full trace capability</strong>\u{202F}– in the cycle-accurate model, to hunt hard-to-find bugs\u{202F} </li>\r\n
</ul>
"""
"overview_cn" => ""
"partnumber" => "Codasip L31AS"
"priority" => 1
"priority_taxo" => 1
"productTypes" => array:1 [ …1]
"provider.id" => 294
"provider.name" => "Codasip"
"provider.object" => "{"id":294,"name":"Codasip","providerslug":"codasip"}"
"provider.priority" => 571
"provider.slug" => "codasip"
"published_as_new_at" => 0
"seofeatures" => """
<ul>\r\n
\t<li>Flexible use cases</li>\r\n
\t<li>roven technology</li>\r\n
\t<li>State-of-the-art safety and security\r\n
\t<ul>\r\n
\t</ul>\r\n
\t</li>\r\n
\t<br />\r\n
\t<br />\r\n
\t<br />\r\n
\t \r\n
\t<li> </li>\r\n
</ul>
"""
"seofeatures_cn" => ""
"shortdescription" => "32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification"
"shortdescription_cn" => ""
"slug" => "32-bit-risc-v-embedded-processor-with-tuv-sud-iso-26262-asil-b-certification"
"sortable_id" => 18735
"taxo0" => array:1 [ …1]
"taxo1" => array:1 [ …1]
"taxo2" => array:1 [ …1]
"taxo3" => array:1 [ …1]
"taxo4" => []
"taxo5" => []
"taxo6" => []
"taxo7" => []
"taxo8" => []
"text_high_priority" => "Codasip L31AS 32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification"
"text_low_priority" => """
The L31AS is a 32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification. Part of our safety and security offering this ideal either as Main Controller or Safety Island in Functional System.\r\n
\r\n
It includes 2 instances the L31 dual-core lockstep configuration along Physical Memory Protection feature.\r\n
\r\n
\r\n
L31AS an in-order 3-stage single-issue core targeted for automotive other functional applications. It based on RV32IMC ISA. physical memory protection. \r\n
\r\n
L31AS features separate Data Instruction AHB-Lite interfaces block-level gating single-core performance counters. uses standard debug specification 4 triggers Debug Interface (DMI) APB interface that can be used to external debuggers. \r\n
\r\n
Certified Safety\r\n
\r\n
The certified by according requirements set forth in ISO26262 up B. delivered pack including manual case report. \r\n
\r\n
Software development\r\n
\r\n
Using AMBA AHB easily connected existing systems interconnects.\u{202F}What more designed simplify software development essential support developers:\u{202F} \r\n
\r\n
\r\n
\tDebug interface\u{202F}– using specification\u{202F}\u{202F} \r\n
\tInstruction-accurate model\u{202F}–\u{202F}for fast execution before hardware available\u{202F} \r\n
\tCycle-accurate algorithm optimization when time constraints require precise execution\u{202F} \r\n
\tFull trace capability\u{202F}– cycle-accurate model hunt hard-to-find bugs\u{202F} \r\n
\r\n
\tFlexible use cases\r\n
\t\r\n
\t\tSafety Island as protected enclave device providing freedom independent safety-related application code. \r\n
\t\tController running code. \r\n
\t\r\n
\t\r\n
\tProven technology\r\n
\t\r\n
\t\tBased silicon-proven embedded processor \r\n
\t\tState-of-the-art verification scheme brings quality reliability \r\n
\t\r\n
\t\r\n
\tState-of-the-art security\r\n
\t\r\n
\t\tDual-core provides robust well trusted approach building high-reliability meeting stringent requirements critical applications \r\n
\t\t\u{200B}L31AS increases against certain threat scenarios help meet certification \r\n
\t\r\n
\t\r\n
"""
"text_medium_priority" => "Processor RISC-V RISCV Microcontroller TuV SuD ISO 26262"
"updated_at" => 1732977234
]
"highlight" => array:1 [
"text_high_priority" => array:2 [ …2]
]
"highlights" => array:1 [
0 => array:3 [ …3]
]
"text_match" => 610246614239412225
"text_match_info" => array:7 [
"best_field_score" => "1108091338752"
"best_field_weight" => 15
"fields_matched" => 1
"num_tokens_dropped" => 0
"score" => "610246614239412225"
"tokens_matched" => 1
"typo_prefix_score" => 0
]
]
]
"out_of" => 18250
"page" => 1
"request_params" => array:4 [
"collection_name" => "product_semiiphub"
"first_q" => "Codasip"
"per_page" => 10
"q" => "Codasip"
]
"search_cutoff" => false
"search_time_ms" => 1
]
]
]
Codasip
IP
