The L11 is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requirements. The core has a 3-stage pipeline and with 16 general purpose registers.
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.
Like with all Codasip RISC-V cores, it is possible to create custom instructions using Codasip Studio to extend the L10 and to generate corresponding hardware and software development kits.
32 bit - Compact RISC-V Processor Core
Overview
Key Features
- 32-bit RISC-V core
- RV32EMC instruction set
- 16 general purpose registers
- Either small sequential multiplier
- 3-stage pipeline
- RISC-V privilege mode support:
- Machine
- Standard RISC-V CLINT
- Up to 256 sources
- Wakeup interrupt controller
- NMI
- On-chip debugger
- RISC-V Debug module
- 2/4 pin JTAG
- 2-8 breakpoints/watchpoints
Benefits
- Flexibility
- Wide choice of configuration options.
- Extensibility
- Ability to create custom RISC-V extensions to optimise performance
- Efficient architectural exploration of custom extensions with Studio
- Automatic HDK and SDK generation from Studio
- Rigorous verification of modified L11 core using UVM
- Tensor Flow Lite Micro is supported
Block Diagram
Applications
- The L11 is aimed at low- to mid-range embedded applications such as IoT, intelligent sensors and wireless
Deliverables
- Human-readable and structured RTL in either:
- Verilog
- VHDL
- System Verilog
- Hardware development kit (HDK)
- Synthesis scripts
- Simulation testbenches
- Debug support
- Software development kit (SDK)
- LLVM C-compiler
- Assembler
- Disassembler
- Linker
- Instruction-accurate simulator
- Cycle-accurate simulator
- Profiler
- Option for extending L11
- CodAL model for Codasip Studio
Technical Specifications
Foundry, Node
Any
Availability
Now