AMBA AHB IP
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AMBA AHB IP
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Verification IP for AMBA AHB
- Complete protocol support for AHB5, AHB3, AHB2, AHB-Lite, and AHB Multi Layer
- Includes primary, secondary, monitor
- Configurable bus model
- Backdoor access to AHB secondary memory
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Simulation VIP for AMBA CHI
- Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
- Generates constrained-random bus traffic with predefined error injection
- Callbacks access at multiple queue points for scoreboarding and data manipulation
- Provides comprehensive checking and coverage model
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Simulation VIP for AMBA CHI-C2C
- Incorporating the latest protocol updates, the Cadence Verification IP for CHI-C2C provides a complete bus functional model (BFM), integrated automatic protocol checks, and a coverage model.
- Designed for easy integration in testbenches at IP, systems with multiple CPUs, accelerators, or other device chiplets, the VIP for CHI-C2C provides a highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms.
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AMBA AHB 3 Lite Verification IP
- The AMBA 3 AHB-Lite Verification IP provides an effective & efficient way to verify the components interfacing with AMBA®3 AHB-Lite bus of an IP or SoC.
- The AMBA 3 AHB-Lite VIP is fully compliant with standard AMBA 3 AHB-Lite specification from ARM.
- This VIP is a light weight VIP with easy plug-andplay interface so that there is no hit on the design cycle time.
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AHB/AXI/Wishbone DMA Controller
- The AXI4-SGDMA IP core implements a Host-to-Peripheral (H2P), or a Peripheral-to-Host (P2H) Direct Memory Access (DMA) engine, which interfaces the host system with an AXI4 Memory-Mapped master port and the peripheral with either a slave or a master AXI4-Stream port.
- The core operates in either Scatter-Gather (SG) Mode, reading descriptors from a run-time defined memory mapped-location, or in Direct Mode, transferring data according to a descriptor stored in local registers.
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Verification IP for AMBA
- AMBA® ACE and CHI coherent interconnect technologies enable an entirely new class of high-performance datacenter applications in areas of machine learning, network processing, storage off-load, in-memory database, and 4G/5G wireless technology.
- Processor architectures and accelerators can now seamlessly operate over cache coherent intercon nects using the right combination of general-purpose processors and heterogeneous acceleration devices, such as FPGAs, GPUs, network/ storage adapters, intelligent networks, and custom ASICs.
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10/100 Mbit Ethernet MAC
- The GRETH core implements a 10/100 Mbit/s Ethernet Media Access Controller (MAC) with AMBA host interface.
- The core implements the 802.3-2002 Ethernet standard. Receive and transmit data is autonomously transferred between the Ethernet MAC and the AMBA AHB bus using DMA transfers.
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CAN 2.0 Controller with DMA
- GRCAN is a CAN 2.0 IP core that implements an internal CAN controller and an AHB DMA backend.
- The APB bus is used for configuration, control and status handling and the AHB bus is used for retrieving and storing CAN messages via the DMA engine.
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AMBA AHB Direct Memory Acess (DMA) Controller
- Multiple independent DMA channels with direct AHB bus interface.
- DMA transfers between AHB memory devices and I/O ports.
- Scatter-gather allows DMA to merge multiple data source to contiguous space.
- Supports both hardware initiated transfer and software initiated transfer.
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AMBA AHB Bus Master
- Supports AHB bus interface to the ARM CPU.
- User interface designed for high speed access to any slave devices on the AHB Bus.
- User specified single or burst data access on the AHB interface and user interface.
- Handles wait state insertion by any slave devices.
