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DDR3 Controller IP

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Compare 6 DDR3 Controller IP from 5 vendors (1 - 6)
  • DDR3 SDRAM Controller
    • Supports industry standard Double Data Rate (DDR2 and DDR3) SDRAM.
    • Pipeline access allows continuous data bursting and hidden command execution.
    • Page hit detection supports fast column access and multiple open banks.
    • High speed implementation with standard DFI support for hard DDR PHY.
    Block Diagram -- DDR3 SDRAM Controller
  • DDR-I/II/III CONTROLLER IP CORE
    • Compliant with JEDEC Standard.
    • Support up to 4 Gb and 8 banks of DDR2 devices.
    • Application bus – FIFO, AHB, Avalon. Support multiple agents on application bus interface with built-in credit/aging based weighted round robin arbitration scheme.
    • Programmable CAS latency and DRAM timing parameters.
    Block Diagram -- DDR-I/II/III CONTROLLER IP CORE
  • DO-254 AXI 7-Series DDRx (Limited) 1.00a
    • DDR3 SDRAM Features
    • Component support for interface widths up to 64 bits
    • Single rank UDIMM and SODIMM support
    • DDR3 (1.5 V) and DDR3L (1.35 V)
  • DO-254 DDR Memory Controller 1.00a
    • DDR, DDR2, DDR3, and LPDDR (Mobile DDR) memory standards support
    • Up to 800 Mb/s (400 MHz double data rate) performance
    • Up to four MCB cores in a single Spartan-6 device
    • Configurable dedicated multi-port user interface to FPGA logic
  • DDR3 Controller IP
    • o High memory throughput achieved via Parallel operation of all the banks and reordering of commands in the controller to ensure the maximum utilization of the DDR Memory
    • o Pipelined operation across the complete design to ensure the highest performance
    • o DDR Interface
    • o Supports all standard DDR3 (x4,x8,x16) SDRAMs
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