DDR3L Synthesizable Transactor provides a smart way to verify the DDR3L component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's DDR3L Synthesizable Transactor is fully compliant with standard DDR3L Specification and provides the following features.
DDR3L Synthesizable Transactor
Overview
Key Features
- Supports 100% of DDR3L protocol standard 8Gb DDR3L.pdf
- Supports all the DDR3L commands as per the specs
- Supports up to 8 GB device density
- Supports 8 internal banks
- Supports following devices:
- X4
- X8
- X16
- Supports all speed grades as per specification
- Supports on-the-fly for burst length
- Supports programmable burst lengths: 4, 8
- Supports write leveling
- Supports programmable write latency and read latency
- Supports both 8 and 16 programmable burst lengths
- Supports the following burst type:
- Sequential
- Interleave
- Supports burst order
- Checks for following:
- Check-points include power on, initialization and power off rules
- State based rules, active command rules
- Read/Write command rules etc
- All timing violations
- Supports DLL features
- Supports self refresh and power down operation
- Supports all mode register programming
- Supports write data mask
- Supports power down features
- Supports output driver calibration
- Supports automatic self refresh(ASR)
- Supports self refresh mode
- Supports self refresh temperature (SRT)
- Supports multipurpose register
- Supports nominal and dynamic ODT (on-die termination) for data, strobe and mask signals
- Supports all types of timing and protocol violation detection
- Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
Block Diagram
Deliverables
- Synthesizable transactors
- Complete regression suite containing all the DDR3L testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation contains User's Guide and Release notes