DDR3 Controller

Overview

The DDR3 controller core is designed for high memory throughput, high clock rates, and full programmability in computing and networking applications.

How a DDR3 Interface Subsystem works

The Rambus DDR3 controller maximizes memory bus efficiency via Look-Ahead command processing, bank management, auto-precharge and additive latency support. The core is DFI compatible and supports a range of interfaces to user logic. The Rambus DDR3 controller can be paired with 3rd-party or customer PHY solutions.

Key Features

Maximizes bus efficiency via look-ahead command processing, bank management, auto-precharge and additive latency support
Latency minimized via parameterized pipelining
Achieves high clock rates with minimal routing constraints
Supports full-rate and half-rate clock operation
Multi-mode controller support
Full run-time configurable timing parameters and memory settings
Supports ODT, dynamic ODT, 2T timing and write leveling calibration
DFI compatible
Full set of Add-On cores available
Minimal ASIC gate count
Broad range of ASIC and FPGA platforms supported
Delivered fully integrated and verified with target PHY

Block Diagram

Deliverables

Core (source code)
Testbench (source code)
Complete documentation
Expert technical support
Maintenance updates

Technical Specifications

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