DDR3 3DS Synthesizable Transactor provides a smart way to verify the DDR3 3DS component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's DDR3 3DS Synthesizable Transactor is fully compliant with standard DDR3 3DS Specification and provides the following features.
DDR3 3DS Synthesizable Transactor
Overview
Key Features
- Supports 100% of DDR3 3DS protocol standard JESD79-3-3
- Supports all the DDR3 3DS commands as per the specs
- Supports up to 64GB device density
- Supports 64 internal banks
- Supports following device type:
- X4
- X8
- Supports all speed grades as per specification
- Supports write pattern command
- Supports CA parity
- Supports programmable write latency and read latency
- Supports on-the-fly for burst length
- Supports programmable burst length: 4, 8
- Checks for following
- Check-points include power up initialization and power off rules
- State based rules, active Command rules
- Read/Write command rules etc
- All timing violations
- Supports all mode register programming
- Supports write data mask
- Supports power down features
- Supports DLL
- Supports write leveling
- Supports ZQ calibration
- Supports self refresh mode
- Supports ODT (On-Die Termination)
- Supports both synchronous and asynchronous on-die termination modes
- Supports all types of timing and protocol violation detection
- Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
Block Diagram
Deliverables
- Synthesizable transactors
- Complete regression suite containing all the DDR3 3DS testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation contains User's Guide and Release notes