IP Catalog > Interface IP > Interconnect IP > MIPI IP > MIPI Controller IP > MIPI UniPro IP > Simulation VIP for MIPI UniPro

Simulation VIP for MIPI UniPro

Overview

In production since 2011 on dozens of production designs.

Incorporating the latest protocol updates, the mature and comprehensive Cadence® Verification IP (VIP) for the MIPI ® UniProsm Protocol provides a complete bus functional model (BFM), integrated automatic protocol checks, coverage model, and compliance tests. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for UniPro helps you reduce time to test, accelerate verification closure, and ensure end-product quality. Our VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported Specifications: MIPI UniPro v1.6, v1.8 and v2.0 and M-PHY v4.0, v4.1, and v5.0.

Key Features

  • Serial and RMMI Interfaces
    • Supports Serial and RMMI interfaces (downstream)
  • CPort Signal Interface
    • Supports CPort signal interface (upstream)
  • All Layers Supported
    • Supports PHY Adapter, Data Link, Network, and Transport layers
  • Built-In Sequences
    • PA link start up, (re-)initialization, configuration, error-recovery, and hibernate enter/exit sequences
  • Data Link Layer
    • Supports DLL initialization, TC0 and TC1, flow control, and acknowledgment mechanisms
  • Transport Layer
    • Supports TL connection management and addressing, segmentation and reassembly, end-to-end flow control, and multi-CPort arbitration
  • Lane Capabilities
    • Supports up to four lanes, PWM G1-G7, HS G1-G5 in each direction, and A/B HS rate series
  • Connectivity Capabilities
    • Supports testing of 1.6, 1.61, 1.8, and 2.0 connection compatibility
  • PHY Testing
    • Complete support of test mode
  • Test Feature
    • Supports complete test feature functionality
  • CDR
    • Supports Clock Data Recovery

    Block Diagram

    Simulation VIP for MIPI UniPro Block Diagram

    Technical Specifications

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