MIPI Controller IP
MIPI Controller IP cores manage the flow of data between processors and peripherals, ensuring seamless integration and low-power operation. MIPI Controller IP supports a wide range of MIPI interfaces, such as MIPI CSI-2 IP for camera modules, MIPI DSI IP for display applications, and MIPI UFS IP for storage solutions. Additionally, other MIPI interfaces like MIPI I3C IP, MIPI SLIMbus IP, and MIPI SoundWire IP offer flexible solutions for sensor, audio, and bus communication.
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MIPI Controller IP
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MIPI Controller IP
from 34 vendors
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MIPI CSI-2 IP
- The MIPI CSI-2 IP core is a highly scalable and silicon-agnostic implementation of the MIPI Camera Serial Interface 2 version 4.1 targeting ASIC and FPGA technologies.
- The MIPI CSI-2 implementation enables high-speed, low-power transmission of image data from camera modules to host processors.
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Mipi Unipro Verification IP
- MIPI UniPro VIP is fully compliant with MIPI UniPro Specification 2.0 and MIPI M-PHY Specification 5.0
- Fully supports Transport Layer, Network Layer, Data Link Layer, PHY Adapter Layer and Device Management Entity
- Supports maximum of four Lanes in each direction
- Supports different HS-GEAR or PWM-GEAR in both directions.
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MIPI DSI v2.2 Verification IP
- Compliant to MIPI DSI Specification version 2.2 and MIPI C-PHY Specification version 2.1 with PPI interface.
- Support all Calibration Format & operations
- C-PHY supports MFAA and SFAA for DSI TX and RX respectively for Data Lane Module in command mode.
- C-PHY supports MFAN and SFAN for DSI TX and RX respectively for data Lane Module in video mode.
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MIPI DSI v1.3.2 Verification IP
- Compliant to MIPI DSI Specification version 1.3.2 and MIPI D-PHY Specification version 1.2 with PPI interface.
- Support all Calibration Formats & operations
- D-PHY supports MFAA and SFAA for DSI TX and RX respectively for Data Lane Module in command mode.
- D-PHY supports MFAN and SFAN for DSI TX and RX respectively for Data Lane Module in video mode.
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MIPI CSI-2 with C-PHY Verification IP
- Compliant to MIPI CSI-2 Specification Version 4.0.1 along with MIPI C-PHY Specification Version 2.1 with PPI interface
- Supports upto 32 virtual channels with C-PHY
- C-PHY supports MFEN and SFEN for CSI-2 TX and RX respectively for Data Lane greater than 1
- C-PHY supports MFAA and SFAA for CSI-2 TX and RX respectively for Data Lane 1 module
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MIPI CSI-2
- Fully MIPI CSI-2 standard compliant
- 64 and 32-bit core widths
- Transmit and Receive versions
- Supports 1-8, 9.0+ Gbps D-PHY data lanes
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MIPI DSI2
- Fully MIPI DSI-2/DSI standard compliant
- 64 and 32-bit core widths
- Host (Tx) and Peripheral (Rx) versions
- Supports 1-4, 9.0+ Gbps D-PHY data lanes
- Supports 1-4, 6.0+ Gsym/s C-PHY lane (trio)
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MIPI I3C Master RISC-V based subsystem
- RISC-V based MIPI I3C master interface has been developed to ease sensor system design architectures in mobile wireless products by providing a fast, low cost, low power, two-wire digital interface for sensors
- All the basic functionalities of MIPI I3C master has been proved with Microsemi smart fusion 2 creative development board .In addition the MIPI I3C master supports for both AHB lite and APB Interface
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MIPI DSI DisplayTransmitter IP
- MIPI DSI Transmitter IP is designed to transmit the data to the host processor
- The MIPI DSI-2 provides the mobile industry a standard, robust, scalable, low-power, high-speed, cost-effective interface that supports a wide range of imaging solutions for mobile devices
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Temperature Sensor
- The TS5111 and TS5110 device incorporate thermal sensing capability which is controlled and read over two wire bus
- These device operate on I2C and I3C two wire serial bus interface
- The TS5 designed for Memory Module Applications
- The TS5 device intended to operate up to 12.5 MHz on a I3C Basic Bus or up to 1 MHz on a I2C Bus
- All TS5 devices respond to specific pre-defined device select code on the I2C/I3C Bus
