IP Catalog > Interface IP > MIPI IP > MIPI Controller IP

MIPI Controller IP

MIPI Controller IP cores manage the flow of data between processors and peripherals, ensuring seamless integration and low-power operation. MIPI Controller IP supports a wide range of MIPI interfaces, such as MIPI CSI-2 IP for camera modules, MIPI DSI IP for display applications, and MIPI UFS IP for storage solutions. Additionally, other MIPI interfaces like MIPI I3C IP, MIPI SLIMbus IP, and MIPI SoundWire IP offer flexible solutions for sensor, audio, and bus communication.

All offers in MIPI Controller IP
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Search (387)
Compare 387 MIPI Controller IP from 33 vendors (1 - 10)
  • MIPI I3C Master RISC-V based subsystem
    • RISC-V based MIPI I3C master interface has been developed to ease sensor system design architectures in mobile wireless products by providing a fast, low cost, low power, two-wire digital interface for sensors
    • All the basic functionalities of MIPI I3C master has been proved with Microsemi smart fusion 2 creative development board .In addition the MIPI I3C master supports for both AHB lite and APB Interface
    Block Diagram -- MIPI I3C Master RISC-V based subsystem
  • MIPI DSI DisplayTransmitter IP
    • MIPI DSI Transmitter IP is designed to transmit the data to the host processor
    • The MIPI DSI-2 provides the mobile industry a standard, robust, scalable, low-power, high-speed, cost-effective interface that supports a wide range of imaging solutions for mobile devices
    •  
    Block Diagram -- MIPI DSI DisplayTransmitter IP
  • Temperature Sensor
    • The TS5111 and TS5110 device incorporate thermal sensing capability which is controlled and read over two wire bus
    • These device operate on I2C and I3C two wire serial bus interface
    • The TS5 designed for Memory Module Applications
    • The TS5 device intended to operate up to 12.5 MHz on a I3C Basic Bus or up to 1 MHz on a I2C Bus
    • All TS5 devices respond to specific pre-defined device select code on the I2C/I3C Bus
    Block Diagram -- Temperature Sensor
  • ETSI SSP I3C Interface
    • The I3C interface for the communication of an Smart Secure Platform(SSP), as defined in ETSI using the Smart Secure Platform Common Layer (SCL) protocol
    • The use of the MIPI I3C Basic bus specification provides the ETSI SSP with a multitude of benefits, such as higher data rate, flexible and efficient information exchange, and strong integration of SSP in connected devices
    Block Diagram -- ETSI SSP I3C Interface
  • MIPI SPMI Target Controller

    • The System Power Management Interface is a two wire interface that connects the integrated power controller (PC) of a System-on-Chip (SoC) processor system with one or more Power Management Integrated Circuits(PMIC) voltage regulation systems

    Block Diagram -- MIPI SPMI Target Controller
  • MIPI SPMI HOST CONTROLLER

    • The System Power Management Interface is a two wire interface that connects the integrated power controller (PC) of a System-on-Chip (SoC) processor system with one or more Power Management Integrated Circuits(PMIC) voltage regulation systems

    Block Diagram -- MIPI SPMI HOST CONTROLLER
  • MIPI CSI -2 TRANSMITTER IP -V3
    • MIPI CSI-2 (Camera Serial Interface) Transmitter IP defines an interface between a peripheral device (camera) and host processor (application engine) for mobile applications
    • The MIPI CSI-2 Transmitter IP provides the mobile industry a standard, robust, scalable, low-power, high-speed, cost-effective interface that supports a wide range of imaging solutions for mobile devices
    Block Diagram -- MIPI CSI -2 TRANSMITTER IP -V3
  • MIPI CSI-2 V3 RECEIVER INTERFACE IP
    • The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile applications
    • The MIPI CSI-2 provides the mobile industry a standard, robust, scalable, low-power, high-speed, cost-effective interface that supports a wide range of imaging solutions for mobile devices
    Block Diagram -- MIPI CSI-2 V3 RECEIVER INTERFACE IP
  • MIPI-I3C UVM VIP
    • The MIPI-I3C VIP provides configurable option to select I3C master/secondary master/slave based on the MIPI I3C DUT function as per user specification
    • Our VIP supports both Single Data Rate (SDR) and High Data Rate (HDR) mode operations
    • Our VIP has a Bus Monitor for performing all protocol checks via assertion and functional coverage option
    • The monitor also performs key protocol checks and reports errors for non compliance with Specification
    Block Diagram -- MIPI-I3C UVM VIP
  • Power Management IC - I3C Basic Interface IP
    • Power Management IC (PMIC) is designed for DDR5 RDIMM, DDR5 LRDIMM, DDR5 NVDIMM application
    • PMIC is used for switching and LDO regulators
    • PMIC-I3C Interface used to select suitable power fit for various application environment
    • PMIC device is intended to operate up to 12.5MHz
    Block Diagram -- Power Management IC - I3C Basic Interface IP
×
Semiconductor IP