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MIPI Controller IP

MIPI Controller IP cores manage the flow of data between processors and peripherals, ensuring seamless integration and low-power operation. MIPI Controller IP supports a wide range of MIPI interfaces, such as MIPI CSI-2 IP for camera modules, MIPI DSI IP for display applications, and MIPI UFS IP for storage solutions. Additionally, other MIPI interfaces like MIPI I3C IP, MIPI SLIMbus IP, and MIPI SoundWire IP offer flexible solutions for sensor, audio, and bus communication.

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Search (281)
Compare 281 MIPI Controller IP from 36 vendors (1 - 10)
  • MIPI SWI3S Manager Core IP
    • The SWI3S (SoundWire I3S Interface) Manager Controller Core IP implements the link protocol to communicate in half-duplex fashion to transfer the Audio streams and the Control information together.
    • One or more SWI3S Peripheral IP can be connected specific to the application.
    Block Diagram -- MIPI SWI3S Manager Core IP
  • CSI-2 v2.1 Receiver IP
    •  Fully compliant to MIPI standard
    • Small footprint
    • Functionality ensured with comprehensive verification
    • Product quality proven with silicon
    Block Diagram -- CSI-2 v2.1 Receiver IP
  • MIPI I3C Target Device
    • MIPI I3C Basic Specification v1.2 compiliance
    • Native 32-bit CPU Interface
    • Optional CPU interface wrappers (APB, AHB, AXI)
    • Legacy I2C communication with 7-bit Static Address
    • I3C Single Data Rate (SDR) mode
    Block Diagram -- MIPI I3C Target Device
  • MIPI D-PHY TX PHY and DSI controller
    • Scalability and Flexibility: Supports multiple data lanes for higher aggregate bandwidth, any of the multiple lanes can be configured into Clock Lane
    • High Data Rates: Supports data transmission rates up to 4.5Gbps per lane, allowing for high-resolution displays and smooth refresh rates
    • Energy Efficiency: Optimized for low power consumption, making it ideal for battery-powered devices
    • Complete Solution: Combines the MIPI D-PHY Transmitter PHY and DSI Controller to make it a one-stop solution
    Block Diagram -- MIPI D-PHY TX PHY and DSI controller
  • Verification IP for I3C/I2C
    • A comprehensive memory VIP solution portfolio for I3C and I2C s used by system-on-chip (SoC) and IP designers to ensure comprehensive verification and protocol and timing compliance.
    • Avery Verification IP for Control/Serial Buses implements a complete set of models, protocol checkers and compliance testsuite in 100% native SystemVerilog and UVM.
    Block Diagram -- Verification IP for I3C/I2C
  • SLIMbus Host IP V2.0
    • The MIPI SLIMbus Host v2.0 typically resides in a mobile platform’s application processor and provides two-wire, multipurpose connectivity with multiple audio and another low/mid bandwidth peripheral devices.
    • The SLIMbus Host Controller IP is designed to provide MIPI SLIMbus 2.0 compliant connectivity to an SoC.
    Block Diagram -- SLIMbus Host IP V2.0
  • SLIMbus Device IP Core
    • The SLIMbus v2.0 Device Controller IP is designed to provide MIPI SLIMbus compliant connectivity for a peripheral device, like an audio codec, to a SLIMbus compliant host, like an Applications Processor on a mobile platform, and share the bus bandwidth with other SLIMbus devices that may exist.
    Block Diagram -- SLIMbus Device IP Core
  • RFFE Slave IP Core
    • Compliant with MIPI’s RFFE specification Rev 3.0
    • Small silicon footprint
    • Scalable Implementation
    • Up to 15 Devices can be connected per Bus
    • Low pin count on Interface side (SCLK and SDATA)
    Block Diagram -- RFFE Slave IP Core
  • RFFE Master IP Core
    • Compliant with MIPI RFFE Specification 3.0
    • Delivered in Reuse Methodology Manual (RMM) compliant Verilog RTL format
    • Optionally delivered as a physical design
    • Small footprint
    Block Diagram -- RFFE Master IP Core
  • MIPI SoundWire Slave Controller 1.2
    • MIPI SoundWire®Slave Controller, typically integrated into audio DSP/Codecs or directly into audio peripherals such as Microphones and Amplifiers used in smart phones, tablets and mobile PCs. 
    • The IP when integrated provides SoundWire, a new audio interface to connect to Master typically embedded in Application Processor or Audio Codecs.
    Block Diagram -- MIPI SoundWire Slave Controller 1.2
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