TSMC IP Cores

The A12B400M is a low-power, high-speed analog to digital converter (ADC) intellectually property (IP) design block.

• 12 Bit
• TSMC
• 12nm
• FFC

The A12B200M is a low-power, analog to digital converter (ADC) intellectually property (IP) design block.

• 12 Bit
• TSMC
• 28nm
• HPC+

The DeepSub™ pPLL05 is a low power, low voltage all digital PLL featuring low-jitter and compact area.

• TSMC
• 6nm
• N6

This DDR3/4 IP combo solution presented, is meticulously designed for high performance and low power consumption, utilizing sophi…

• Controller + 2
• DDR3 + 1
• TSMC
• 12nm
• FFC
• Available on request

Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…

• TSMC
• 3nm
• N3P

Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…

• TSMC
• 5nm
• N5A

The multi-channel PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across back…

• Controller + 1
• PCIe Gen7
• TSMC
• 3nm
• N3P
• Available on request

This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 7, 15 or 31 order, up to 32Gbps.

• TSMC
• 28nm

055TSMC_OSC_01 is a reference frequency generator designed to form a reference signal in the frequency range from 10 to 50MHz.

• TSMC
• 55nm
• GP
• Silicon Proven

Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband proce…

• MIPI C-PHY + 1
• TSMC
• 5nm
• N5A

The Ceva-Waves Links100 is a low-power multi-protocol wireless connectivity IoT platform combining a cost-optimized Wi-Fi 6 1×1 4…

• TSMC
• 22nm
• ULL
• In Production

your custom Switch Fabric, AI, or HPC ASIC with Credo’s SerDes IP.

• TSMC
• 12nm
• FFC
• Silicon Proven

This LPDDR5X PHY is a memory-side interface IP normally found implemented within commodity DRAM products.

• Controller + PHY + 1
• LPDDR5X
• TSMC
• 7nm
• N7+

This LPDDR5 PHY is a memory-side interface IP normally found implemented within commodity DRAM products.

• Controller + PHY + 1
• LPDDR5
• TSMC
• 7nm
• N7+
• Available on request

This LPDDR4X PHY is a memory-side interface IP normally found implemented within commodity DRAM products.

• Controller + PHY + 1
• LPDDR4
• TSMC
• 7nm
• N7+
• Available on request

The Synopsys High-Bandwidth Interconnect PHY IP enables high bandwidth, low-power and low-latency die-to-die connectivity in a pa…

• TSMC
• 5nm
• N5FF
• Available on request

The Synopsys XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interface…

• TSMC
• 5nm
• N5FF
• Available on request

Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…

• TSMC
• 6nm
• N6

Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…

• TSMC
• 3nm
• N3E

The silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE…

• TSMC
• 28nm
• Available on request