Analog IP for TSMC

Compare 277 Analog IP for TSMC from 29 vendors (1 - 10)

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28nm

32Gbps, 31 order, Pseudo Random Bit Sequence Generator / Checker
- PRBS order: 31 based on formula: X1=X28^X31
- Full bit rate at input and output up to 32Gbps
- Generator, Checker and Counter functions
- Accurate error count: no omissions or double counts
32Gbps Pseudo Random Bit Sequence Generator/Checker
- PRBS order: 7 or 15 based on formulas: X1=X6^X7; X1=X14^X15
- Full bit rate at input and output up to 32Gbps
- Generator, Checker and Counter functions
- Accurate error count: no omissions or double counts
- Full rate CMOS differential input data, centered with half-rate CMOS differential clock
- Full rate CMOS differential output data, aligned with half-rate CMOS differential clock
- Asynchronous low frequency CMOS control interface
- Supply voltage: 0.9V
32Gbps, 7/15/31 order, Pseudo Random Bit Sequence Generator/Checker
- PRBS order: 7, 15 or 31 based on formulas: X1=X6^X7; X1=X14^X15; X1=X28^X31
- Full bit rate at input and output up to 32Gbps
- Generator, Checker and Counter functions
- Accurate error count: no omissions or double counts
- Full rate CMOS differential input data, centered with half-rate CMOS differential clock
- Full rate CMOS differential output data, aligned with half-rate CMOS differential clock
Data Converter - 12bit 2MSps SAR ADC(TSMC CLN28HPC+)
- Conversion method : Successive approximation
- Resolution : 12bit
- Conversion time : 0.5us
- Differential nonlinearity : -1LSB(Min.)/+2LSB(Max)
Data Converter - 12bit 2MSps SAR ADC (TSMC CLN28HPM/HPC)
- Process : TSMC CLN28HPM/HPC
- Available metallization technologies :4X2Y2R+AP-RDL
Analog-PLL For Spread Spectrum Clock
- TSMC 28nm HPM/HPC
- Including Loop-filter
- VCO operating range : 900MHz - 1800 MHz
Analog PLL For Frequency Multiplying
- Including Loop-filter
- VCO operating range : 2500MHz - 5000 MHz
- Output frequency range : 1250MHz - 2500 MHz
Analog-PLL For Frequency Multiplying
- Process: TSMC 28nm HPM/HPC
- Available metalization technologies: 4X2Y2R and 5X2Y2R
6-bit, 1 GSPS High Performance DAC in 28nm CMOS
- 6-bit resolution, update rate up to 1 GSPS
- Fully differential current output, fully specified from -40C to 125C
- Ultra low power dissipation
- Wide output bandwidth
High Performance Fractional-N RF Frequency Synthesizer PLLs for 5G, WiFi, etc
- Fractional-N digital PLL architecture, using an LC-tank oscillator