Analog IP for TSMC

Compare 240 Analog IP for TSMC from 27 vendors (1 - 10)

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28nm

32Gbps, 31 order, Pseudo Random Bit Sequence Generator / Checker
- This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 31 order, up to 32Gbps. Error count is accurate: no double counts or omissions regardless of error sequence or frequency of occurrence.
- Can be used as Generator, Checker or both. No inductors are used minimizing area and EM interference. Simple control interface, with low frequency asynchronous signals only.
6-bit, 1 GSPS High Performance DAC in 28nm CMOS
- 6-bit resolution, update rate up to 1 GSPS
- Fully differential current output, fully specified from -40C to 125C
- Ultra low power dissipation
- Wide output bandwidth
TVM - Temperature/Voltage Monitor in 28nm CMOS
- 22µA nominal supply current at 900Hz throughput
- <500nA nominal supply current at 10Hz throughput
- ± 4C temperature accuracy without trim
- ± 1C temperature accuracy after single room temperature trim
TSMC 28HPC+ Process Monitor
- Supply 0.9V
- SVT, HVT and ULVT P and N devices
Process/Voltage/Temperature Sensor (Supply voltage 1.8V/0.9V)
- TSMC 28nm 28HPC CMOS
- High accuracy temperature and voltage measurements
- Process detector for all-voltage threshold MOS transistors
- Up to 16 remote temperature/voltage sensors
PVT SENSOR
- SGC21713_IP007708_GF_22FDX can be used in a control loop to minimize the voltage for a given frequency or maximize frequency for a given voltage
- Based on a group of sensors, it permits PVT and aging tracking, while allowing the identification of the actual variable that changed
- Designed to achieve 3% overall accuracy (over Load / Line / Temp), it is specified from TJ = –40°C to +125°C.
Temperature Sensor (Digital Output)
- Measurement Range: -20°C to +100°C
- Uncalibrated Accuracy: ±6°C
Sleep Management Subsystem
- Power-On-Reset
- Programmable relaxation oscillator
- Low Power Comparator
Power Management Subsystem
- The agilePMU Subsystem is an efficient and highly integrated Power Management Unit for SoCs/ASICs.
- Featuring a Power-On-Reset (POR), multiple Low Drop-Out (LDO) regulators, and an associated reference generator.
- The agilePMU Subsystem is designed to ensure low power consumption while providing optimal power management capabilities.
Sensor Interface Subsystem
- The agileSensorIF Subsystem is an efficient and highly integrated sensor interface for SoCs/ASICs.
- Featuring multiple Analog-to-Digital Converters (agileADC), Digital-to-Analog Converters (agileDAC), low-power programmable analog comparators (agileCMP_LP), and an associated reference generator (agileREF).
- The agileSensorIF Subsystem enables easy interaction with the analog world.