32Gbps, 31 order, Pseudo Random Bit Sequence Generator, Checker, Error Counter

Overview

Key Features

• PRBS order: 31 based on formula: X1=X28^X31
• Full bit rate at input and output up to 32Gbps
• Generator, Checker and Counter functions
• Accurate error count: no omissions or double counts
• Full rate CMOS differential input data, centered with half-rate CMOS differential clock
• Full rate CMOS differential output data, aligned with half-rate CMOS differential clock
• Asynchronous low frequency CMOS control interface
• Supply voltage: 0.9V
• Typical power consumption: 70mA at 32Gbps in simultaneous Generator and Checker mode; scales with bit rate
• Power down mode
• Error counter ready indicator signal
• Operational temperature range: -40C to +110C
• Footprint: 65 x 70 um
• Process: TSMC 28nm HPC/HPC+, portable to more advanced processes

Benefits

• Direct high-speed PRBS generation and checking
• Embedded accurate Error Counter
• Compact footprint, no inductors, minimal EM interference
• Simple, asynchronous interface, easy transition between clock domains
• Easily portable to more advanced technology
• Facilites faster implementation of advanced flexible built-in self-test (BIST)
• Reduces the need of expensive testing equipment
• Eliminates on-wafer high-speed test

Block Diagram

Applications

• Testing of communication channels and clock/data recovery systems
• High data rate Pseudo Random Bit Sequence generation
• Internal loop-back - on-chip test
• External loop-back - for channel characterization and qualification
• Key part of built-in self-test (BIST) for CDR, SerDes, Re-clockers

Deliverables

• Technical Brief - TB
• Data Sheet - DS
• Application Note - AN
• Models: Verilog-AMS, Spectre (CC extracted), Spectre (back-annotated)
• Demo Testbenches - DTB (OA schematics)
• GDSII Black Box
• GDSII

Technical Specifications