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Receiver/Transmitter IP for TSMC

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Compare 11 Receiver/Transmitter IP for TSMC from 3 vendors (1 - 10)
  • LVDS Deserializer IP
    • The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology.
    • Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The De-serializer is highly integrated and requires no external components.
    Block Diagram -- LVDS Deserializer IP
  • Camera Combo Receiver - 2.4Gbps 8-Lane - TSMC 28nm HPC
    • The CL12832M8R2JM3KIP2400 is designed to support data rate in excess of maximum 2.4Gbps utilizing SLVS-EC / sub-LVDS / CMOS 1.8V interface specification.
    • The CL12832M8R2JM3KIP2400 can change Interface type to same PAD for changing mode.
  • MIPI D-PHY Transmitter 4-Lane (4-Data/1-Clock) 250Mbps
    • The CL12631I4T1AS1BIP2500 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to Host System.
    • The CL12631I4T1AS1BIP2500 converts the input parallel data to the serial data and output it.
    • The CL12631I4T1AS1BIP2500 is designed to support maximum 2.5Gbps data rate utilizing mipi-DPHY_specification_v1-2.
  • MIPI D-PHY/sub-LVDS Transmitter - 8-Lane 2.5Gbps - TSMC 28nm HPC+
    • The CL12661M8T1KM2JIP is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to Host System.
    • The CL12661M8T1KM2JIP is designed to support data rate in excess of maximum 2.5Gbps utilizing sub-LVDS / MIPI-DPHY interface specification.
  • Camera Combo Receiver - 2.4Gbps 8-Lane - TSMC 28nm HPC
    • The CL12842M8R2JM4TIP2500 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processer) and DSP.
    • The CL12842M8R2JM4TIP2500 is designed to support data rate in excess of maximum 2.5Gbps utilizing SLVS-EC / sub-LVDS / MIPI D-PHY v-1.2/ CMOS 1.8V interface specification.
  • Camera 6/7-mode Combo Receiver - 1G/1.5Gbps
    • The CL12684KM4-8-12-16R3AM6-7ZIP is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to Host System.
    • The CL12684KM4-8-12-16R3AM6-7ZIP is designed to support data rate in excess of maximum 1Gbps utilizing sub-LVDS / mini-LVDS / LVDS / HiSPi(SLVS-400, HiVCM) / MIPI-DPHY / CMOS-1.8V / CMOS-3.3V interface specification.
  • Dual FPD-link, 30-Bits Color LVDS Receiver, 170Mhz (SVGA/FHD@120Hz) LVDS de-serializer 10:70 channel decompression with automatic de-skew
    • Layout structure based on 0.13um Logic 1P6M, 1P7M, or 1P8M Salicide 1.2V/3.3V process.
    • 1.2V/3.3V ±10% supply voltage, -40/+125°C
    • Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3- 1996+ ANSI/TIA/EIA-644-A Specifications.
    • Up to 11.9Gbps bandwidth (40 to 170Mhz pixel clock) per pixel channel (Full HD @ 120Hz)
  • Dual RSDS Transmitter, 30-bit color, 80-400Mb/s (SVGA/Full HDTV@120Hz)
    • • 40 to 200 Mhz Pixel rate per channel ( 80 to 400 Mb/s SDR input, 80 to 400 Mb/s DDR output)
    • • 30 DATA + 9 RSDS CLK channels
    • • Complies with RSDS “Intra-Panel” Interface Specification rev1.0, May 2003.
    • • 1P6M layout structure based on 0.13um 1P6M generic logic process.
  • Dual RSDS Transmitter, 30-bit color, 40-300Mb/s (SVGA/UXGA/full HDTV) LCD & Plasma display
    • • 20 to 150 Mhz Pixel rate per channel ( 40 to 300 Mb/s SDR input, 40 to 300 Mb/s DDR output )
    • • 30 DATA + 9 RSDS CLK channels
    • • Complies with RSDS “Intra-Panel” Interface Specification rev1.0, May 2003.
    • • 1P6M layout structure based on 0.18um 1P6M generic logic process.
  • Dual RSDS Transmitter, 24/18-bit color, 40-300Mb/s (SVGA/UXGA/full HDTV) LCD & Plasma display
    • • 20 to 150Mhz Pixel rate ( 40 to 300 Mb/s SDR input, 40 to 300 Mb/s DDR output)
    • • Complies with RSDS “Intra-Panel” Interface Specification rev1.0, May 2003.
    • • 1P6M layout structure based on 0.18um 1P6M generic logic process.
    • • 3.3V/1.8V 10% supply voltage, -40/+125C
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