Camera Combo Receiver - 2.4Gbps 8-Lane - TSMC 28nm HPC

Overview

Key Features

• SLVS-EC ver.1.2 / MIPI D-PHY ver.1-2 compliant
• Supporting for four kind Differential Input Signals
  • 1) SLVS-EC (Maximum 2.4Gbps)
  • 2) sub-LVDS (Maximum 800Mbps)
  • 3) MIPI D-PHY (Maximum 2.5Gbps)
  • 4) CMOS 1.8V (Maximum 166MHz)
• Xtal Input Clock Frequency Selectable 24MHz / 37.125MHz / 54MHz / 72MHz
• Maximum Input Clock Frequency ~1.25GHz, Maximum Input Data Transfer Rate ~2.5Gbps
• Maximum Output Clock Frequency ~312.5MHz
• Power Supply : Vcc=1.8V (IO and Analog) Vdd=0.9 V (Inside Core)
• Maximum Lane Number : 8-Lane
• 10-bit/Lane Parallel Outputs (SLVS-EC)
  • 8-bit/Lane Parallel Outputs (sub-LVDS Serial / MIPI D-PHY)
  • 1-bit/Lane Parallel Outputs (sub-LVDS Parallel)
• Including Power Down Mode
• Including "Hi-Z" Detect Circuit for SLVS-EC
• TSMC 28nm HPC Process 1P10M5X2R (Using of Standard Vth Transistor)
• Poly Direction: South-North
• Various process porting support available ( Please contact us. )
• Supporting Link-layer: CD12842M8LRM3BM4AIP312P5(SLVS-EC/LVDS, CSI2 Combo) soft macro

Technical Specifications