Special IP for TSMC
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84
Special IP
for TSMC
from 8 vendors
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10)
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1.0-3.3V GPIO With I2C Open Drain And 3.3V & 5V Analog Cells in 55nm
- 1.0V-3.3V | 3.3V IO operation
- Dual independent IO rails
- Output enable / disable (HiZ when disabled)
- Power-down control (HiZ upon VDD disable)
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A 180nm Flip-Chip IO library with 1.2-1.8V GPIO, 1.8V & 5V analog/RF, 20-36V ultra-low leakage low-cap HV analog and OTP program cell
- GPIO:
- ANALOG
- OTP Programming Cell
- Physical Attributes
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5MHz-35MHz Low Power Crystal Oscillator
- 4MHz-35MHz Frequency range.
- No external bias or limit resistors required.
- Current optimization for best power at frequency.
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TSMC 3nm (N3E) 1.8V SD/eMMC IO
- Completely hardened PHY solution along with programmable delay chains & I/Os
- Fully selectable output impedance
- Compliant with eMMC 5.1 (JESD84-B51A) and SDIO 3.0 JEDEC Standard
- Automotive G1/G2 supported, ASIL-B certified
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Small area rail clamp for FinFET
- Power clamp ESD solutions
- Rail clamp ESD protection
- 0.75V domain
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Analog I/O - low capacitance, low leakage
- Scalable robustness
- Area efficient
- low capacitance option
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on-chip ESD protection
- Analog I/Os
- ESD Power protection
- Ground pads
- ESD protection cells
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On-chip protection against IEC61000-4-2 events
- Analog Pads
- Power Pads
- Ground Pads
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I/O LIbrary
- Schmitt triggered input
- pull up/down control modes
- Slew rate controled output