A radiation-hardened TSMC 130nm Wirebond I/O Library with 3.3V GPIO, 3.3V LVDS TX & RX, 3.3V I2C ODIO, 3.3V Analog cell, OTP cell, and associated ESD.
Key attributes of this silicon-proven, radiation hardened I/O library include an extended operational temperature range (-50C to 200C), a sleep retention mode, and a built in power regulation PMOS device for core VDD. The GPIO cell can be configured as input, output or open drain with an optional internal 60K ohm pull up or pull down resistor and a selectable Schmitt trigger. Cells for IO core power and ground with built in ESD are included. 3.3V LVDS transmit receive cells, along with 3.3V programming, 3.3V I2C/SMBUS open drain and analog cells (and associated ESD) complement the GPIO offering. The library is enriched with feed through, filler, corner and domain break cells to allow for flexible pad ring construction. ESD design levels are 2KV HBM and 500V CDM.
Operating Conditions GPIO Block Diagram
| Parameter | Value |
| VDDIO | 3.3V |
| Core VDD | 1.5V |
| BEOL | 1P8M_6x1z |
| Temperature | -50C to 200C |
| Cell Size | 140um x 235um |
| Pitch | 140um single |
| ESD | 2kV HBM & 500V CDM |
Cell Summary
| Cell Type | Feature |
| Supply/ESD | 3.3V; 1.5V; GND |
| GPIO | 50MHz (15pF) |
| I2C ODIO | 3.3V |
| LVDS | 3.3V TX & RX |
| Analog | 3.3V |
| OTP | 3.3V |
| Break Cells | VDDIO, VDD |
| Filler Cells | 1um, 5um digital & analog |
