Wirebond Digital and Analog Library in TSMC 65nm

Overview

A mixed Digital and Analog Library, compatible with I2C and I3C Protocols.

This library is a mixed Digital and Analog library built for the TSMC 65nm process. It is based around a Fail-Safe General Purpose Input/Output (FSGPIO) cell that is compatible with both I2C and I3C protocols. The FSGPIO operates with a power supply of 1.0 to 1.2V and can tolerate external signals up to 3.3V. The library contains all the power, ground, and ESD cells to support the FSGPIO as well as an Analog I/O cell. The cells are laid out in an inline wirebond format.

Operating Conditions

Parameter Value
VDDIO 1.0V/1.1V/1.2V
AVDD18 1.8V
Core VDD 1.2V
Tj -40C to 125C
ESD HBM +4kV
ESD CDM +500V
Latchup 200mA

Cell Size and Metal Stack

Cell Size Metal Stack
Bondpad 60x60um  
I/O 125x100um 1P7M

Library Cell Summary

Cell Type Feature
FSGPIO Compatible with I2C and I3C
TEST IO Compact GPIO for testing
VDD SW Low-impedance switch

Key Features

  • Full compliance with I2C, I3C, 1.8V, 2.5V and 3.3V specs
  • Supports standard I3C, High-speed I3C, and Ultra-High-Speed I3C modes
  • Push-pull operation in I3C mode
  • Supports   I2C  standard   mode,   fast  mode,   fast mode plus, high-speed mode
  • Open Drain operation in I2C mode, up to 3.3V
  • 3 options for on-die termination to VDDIO: 500 ohms, 1k ohms, and 2k ohms
  • 50k ohm active pull-down
  • High-speed data transfer rate up to 13MHz for I3C
  • Low power consumption
  • 3.3V tolerance on a 1V power supply
  • Bi-Directional data communication
  • Automatically   detects  bus  voltage  and  switches   input thresholds

Block Diagram

Wirebond Digital and Analog Library in TSMC 65nm Block Diagram

Technical Specifications

Foundry, Node
TSMC 65nm
TSMC
Pre-Silicon: 65nm G
×
Semiconductor IP