Multi-Protocol PHY IP for TSMC

Compare 6 Multi-Protocol PHY IP for TSMC from 1 vendors (1 - 6)

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112G VSR PHY, TSMC N3P x2, North/South (vertical) poly orientation
- Supports 1.25 to 112 Gbps data-rate
- Supports PCI Express 6.0, 1G to 400G/800G Ethernet, CCIX, CXL, JESD204C, CPRI, SATA, and OIF CEI LR/MR/VSR Electrical Interfaces protocols
- Supports x1 to x16 macro configurations with aggregation and bifurcation
- Spread Spectrum Clock (SSC) support for PCIe
112G PHY, TSMC N3P x4 1.2V, North/South (vertical) poly orientation
- Supports 1.25 to 112 Gbps data-rate
- Supports PCI Express 6.0, 1G to 400G/800G Ethernet, CCIX, CXL, JESD204C, CPRI, SATA, and OIF CEI LR/MR/VSR Electrical Interfaces protocols
- Supports x1 to x16 macro configurations with aggregation and bifurcation
- Spread Spectrum Clock (SSC) support for PCIe
112G LRM PHY, TSMC N3P x4, North/South (vertical) poly orientation
- Supports 1.25 to 112 Gbps data-rate
- Supports PCI Express 6.0, 1G to 400G/800G Ethernet, CCIX, CXL, JESD204C, CPRI, SATA, and OIF CEI LR/MR/VSR Electrical Interfaces protocols
- Supports x1 to x16 macro configurations with aggregation and bifurcation
- Spread Spectrum Clock (SSC) support for PCIe
224G Ethernet PHY in TSMC (N3E)
- Optimized for performance, power, and area
- Includes one, two, or four full-duplex PAM-4/6 transceivers (transmit and receive functions)
- Supports IEEE and OIF-CEI-224G standards
- Includes auto-negotiation and link training capabilities
32G PHY in TSMC (N5A, N3A) for Automotive
- Includes one, two, four, eight or sixteen full-duplex transceivers (transmit and receive functions)
- Supports back channel initialization, aggregation, bifurcation, and power management
- Supports both internal and external reference clock connections to the PHY
- Configurable transmitter and receiver equalization, supporting chip-to-chip, port side, backplane interfaces
32G PHY in TSMC (16nm, 12nm, N7, N6, N5, N5A, N3E. N3P)
- Includes one, two, four, eight or sixteen full-duplex transceivers (transmit and receive functions)
- Supports back channel initialization, aggregation, bifurcation, and power management
- Supports both internal and external reference clock connections to the PHY
- Configurable transmitter and receiver equalization, supporting chip-to-chip, port side, backplane interfaces