PLL IP for TSMC
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- 16nm
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Wide Range Programmable Integer PLL on TSMC CLN16FFC
- Electrically Programmable PLL for multiple applications
- Wide Ranges of Input and Output Frequency for diverse clocking needs
- Implemented with Analog Bits’ proprietary architecture
- Fully integrated inside customer-specified IO ring
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LVDS 160MHz 8-Lane PHY TX IP on TSMC 16FFC
- The CL12491M8TIP160 transmitter converts parallel RGB data and 4bits of HYNC,VSYNC,DE and Control) of CMOS parallel data into serial LVDS data streams.
- A phase-locked clock is transmitted in parallel with the data streams over a dedicated LVDS link.
- The polarity of differential signals for each data lane can be controlled.
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3GHz, low jitter fractional-N, Digital PLL, TSMC 16FFC, N/S orientation
- Pure core voltage design
- Compact IP size (< 0.013mm²) and low power consumption (1.1mW @ 3GHz)
- Compatible with commonly used crystal oscillator frequencies
- Good power noise immunity for period jitter (< ±15%/V)
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4.8GHz low jitter fractional-N, Digital PLL, TSMC 16FFC, N/S orientation
- Pure core voltage design
- Compact IP size (< 0.013mm²) and low power consumption (1.1mW @ 3GHz)
- Compatible with commonly used crystal oscillator frequencies
- Good power noise immunity for period jitter (< ±15%/V)
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Ultra-Low Power Fractional PLL IP in in TSMC (12/16nm FFC, 22nm ULP/ULL, 28nm HPC+)
- Supports wide input frequency range: 10MHz to 240MHz
- Supports 3:1 output frequency range allows optimization for power and jitter performance
- 24-bit fractional accuracy
- Supports Spread Spectrum Clocking
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Low Power Fractional PLL IP in TSMC(12/16nm FFC, 22nm ULP/ULL, 28nm HPC+)
- Compact IP size ( smaller than 0.01mm²) and low power consumption ( < 2.7mW @ 3.5GHz )
- Compactible with commonly used crystal oscillator frequencies
- Good power noise immunity for period jitter ( < +-15ps )
- Support 24-bit fractional accuracy
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14GHz Integer-N High-Speed PLL
- Type II hybrid Integer-N LC-PLL
- Quadrature clocks at 14GHz and 7GHz
- Fast locking
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Fractional-N PLLs for Performance Computing
- Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 4GHz
- Reference clock from 10MHz to 500MHz
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Fully Digital Glitch Free PLL TSMC 16FFC 16 nm - 300-3000 MHz
- Ideal as a clock generator for digital design
- Excellent frequency jitter performance
- Ultra-low area fully digital PLL design
- Patented glitch free frequency adjustment
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Low Voltage, Low Power Fractional-N PLLs
- Low power, suitable for IoT applications
- Good jitter, suitable for clocking digital logic.
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
