Low Power Fractional PLL IP in TSMC(12/16nm FFC, 22nm ULP/ULL, 28nm HPC+)
Overview
M31 LPFPLL is a low-power programmable fractional-N (LPF), phase-locked loop (PLL) for frequency synthesis. It can support a wide range of output frequency with fine resolution, as well as supporting multiple input reference frequencies. M31 LPFPLL is ideal for the use in noisy ASIC/SoC environment due to the excellent supply noise immunity. Lockdetect flag supports real-time monitoring of the phase-locked status. With embedded ESD power clamp circuits and internal initial sequence applied to release from complex configurations and settings, M31 LPFPLL is available as a single macro and can be integrated into any ASIC/SoC easily
Key Features
- Compact IP size ( smaller than 0.01mm²) and low power consumption ( < 2.7mW @ 3.5GHz )
- Compactible with commonly used crystal oscillator frequencies
- Good power noise immunity for period jitter ( < +-15ps )
- Support 24-bit fractional accuracy
- Support down spread-spectrum clocking (SSC) technology
- Embedded lock-detect flag
- Embedded frequency meter for mass production test
- Full deliverables to ease ASIC/SoC integration
- Embedded watchdog circuit for automotive application
Block Diagram
Technical Specifications
Foundry, Node
TSMC (12/16nm FFC, 22nm ULP/ULL, 28nm HPC+)
TSMC
Silicon Proven:
12nm
,
16nm
,
22nm
,
28nm
HPCP
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