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Clock Generator PLL IP for TSMC

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Compare 26 Clock Generator PLL IP for TSMC from 4 vendors (1 - 10)
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  • 16nm
  • 14GHz Integer-N High-Speed PLL
    • Type II hybrid Integer-N LC-PLL
    • Quadrature clocks at 14GHz and 7GHz
    • Fast locking
    Block Diagram -- 14GHz Integer-N High-Speed PLL
  • Fractional-N PLLs for Performance Computing
    • Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
    • Extremely small die area (< 0.005 sq mm), using a ring oscillator
    • Output frequency can be from 1 to 400 times the input reference, up to 4GHz
    • Reference clock from 10MHz to 500MHz
    Block Diagram -- Fractional-N PLLs for Performance Computing
  • Fully Digital Glitch Free PLL TSMC 16FFC 16 nm - 300-3000 MHz
    • Ideal as a clock generator for digital design
    • Excellent frequency jitter performance
    • Ultra-low area fully digital PLL design
    • Patented glitch free frequency adjustment
    Block Diagram -- Fully Digital Glitch Free PLL TSMC 16FFC 16 nm - 300-3000 MHz
  • Low Voltage, Low Power Fractional-N PLLs
    • Low power, suitable for IoT applications
    • Good jitter, suitable for clocking digital logic.
    • Extremely small die area (< 0.005 sq mm), using a ring oscillator
    • Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
    Block Diagram -- Low Voltage, Low Power Fractional-N PLLs
  • General Purpose Fractional-N PLLs
    • Low power, suitable for logic clocking applications
    • Extremely small die area, using a ring oscillator
    • Twelve bits fractional resolution
    Block Diagram -- General Purpose Fractional-N PLLs
  • High Performance Fractional-N RF Frequency Synthesizer PLLs for 5G, WiFi, etc
    • Fractional-N digital PLL architecture, using an LC-tank oscillator
    Block Diagram -- High Performance Fractional-N RF Frequency Synthesizer PLLs for 5G, WiFi, etc
  • TSMC CLN16FF+LLLVT 16nm Clock Generator PLL - 600MHz-3000MHz
    • Designed as a very flexible clock multiplier capable of multiplying an input clock from 1 to 4096 with very small period jitter while operating at the highest possible bandwidth.
    • Delivers optimal jitter performance over all multiplication settings.
    • Available with multi-phase outputs and, in some processes, with an I/O voltage regulator.
    • Ideal for system clock generation, SerDes and video clock applications.
  • TSMC CLN16FF+LLLVT 16nm Clock Generator PLL - 300MHz-1500MHz
    • Designed as a very flexible clock multiplier capable of multiplying an input clock from 1 to 4096 with very small period jitter while operating at the highest possible bandwidth.
    • Delivers optimal jitter performance over all multiplication settings.
    • Available with multi-phase outputs and, in some processes, with an I/O voltage regulator.
    • Ideal for system clock generation, SerDes and video clock applications.
  • TSMC CLN16FF+LLLVT 16nm Clock Generator PLL - 1200MHz-6000MHz
    • Designed as a very flexible clock multiplier capable of multiplying an input clock from 1 to 4096 with very small period jitter while operating at the highest possible bandwidth.
    • Delivers optimal jitter performance over all multiplication settings.
    • Available with multi-phase outputs and, in some processes, with an I/O voltage regulator.
    • Ideal for system clock generation, SerDes and video clock applications.
  • TSMC CLN16FF+LL 16nm Clock Generator PLL - 400MHz-2000MHz
    • Designed as a very flexible clock multiplier capable of multiplying an input clock from 1 to 4096 with very small period jitter while operating at the highest possible bandwidth.
    • Delivers optimal jitter performance over all multiplication settings.
    • Available with multi-phase outputs and, in some processes, with an I/O voltage regulator.
    • Ideal for system clock generation, SerDes and video clock applications.
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